Presentation is loading. Please wait.

Presentation is loading. Please wait.

AGENDA Architecture Microprocessor Communication and Bus Timings

Similar presentations


Presentation on theme: "AGENDA Architecture Microprocessor Communication and Bus Timings"— Presentation transcript:

1 AGENDA Architecture Microprocessor Communication and Bus Timings
Demultiplexing Address and Data Lines

2 Architecture of 8085 Reveals the internal logic of a Microprocessor
8085 Architecture consists of following blocks: ALU logic Register Logic Timing and Execution Logic Interrupt Logic Serial I/O Logic

3 Architecture of 8085

4 General Purpose Registers
Register Section General Purpose Registers A, B, C, D, E, H, and L BC, DE, and HL Special Function Registers Program Counter Stack Pointer

5 Flag Register S Z P C X Sign Carry Zero Parity Auxiliary Carry
AC P C Sign Carry Zero Parity Auxiliary Carry X - Unspecified

6 Timing and Control Unit
Timing and Execution Logic Instruction Register Instruction Decoder Timing and Control Unit Control Signals

7 Timing and Execution Logic
Control Signals READY, RD’,WR’,ALE Status Signals S0, S1, IO/M’ DMA Signals HOLD, HLDA RESET Signals RESET IN, RESET OUT

8 Consists of 5 interrupts with following properties:
Interrupt Logic Consists of 5 interrupts with following properties: Priority Maskable and Non Maskable Vectored and Non – Vectored INTA is an output signal

9 Serial I/O Logic Supports serial I/O using 2 lines
SID – Serial Input Data SOD – Serial Output Data

10 Mp communication and Bus Timings
The instruction code (4FH – MOV C, A) is stored in memory location 2005H. Illustrate the steps and the timing of data flow when it is being fetched

11 Mp Communication And Bus Timings
Data Bus 4F Internal Data Bus Memory 2000 B C Instruction Decoder D E ALU H L 2005 4F 2005 SP PC Control Logic Address Bus 4F RD

12 Demultiplexing Address & Data Lines

13 What we studied in this session..
8085 Architecture 8085 Communication and bus timings Demultiplexing Address & Data Lnes

14 Probable Questions.. Explain with a neat diagram, the architecture of 8085 microprocessor Explain the flag register of 8085. With a neat diagram, explain how to separate multiplexed address and data lines in 8085. What Signals are activated when I/O port at address ABCD H is read by 8085 ?

15 Thank You Q & A


Download ppt "AGENDA Architecture Microprocessor Communication and Bus Timings"

Similar presentations


Ads by Google