1. Advanced Logical Effort
Bart Zeydel

2. Logical Effort Outline
Equal Slopes Discussion
Optimal Path Length
Multiple Input paths
Complex Paths
Application to a Real Design
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

3. Prof. V. G. Oklobdzija: High-Performance System Design
Dependent Voltage-Controlled Current Source Modeling of Gate Output Slope
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

4. Prof. V. G. Oklobdzija: High-Performance System Design
Delay Definition Vt
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

5. More Details on Delay Model
Not dependent on Wi
however it is typically negligible
Parasitic Capacitance approximately scales with Wi
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

6. Optimization Discussion
Assume fi = fi+1
Plugging into our slope equation
Only changes with f
Equal stage effort results in equal slopes!
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

7. Prof. V. G. Oklobdzija: High-Performance System Design
LE with Slopes Summary
Using equal stage effort achieves equal slopes
Similarly it can be shown that using equal slopes will result in equal stage effort
Justifies characterization setup
- use equal input and output slopes to obtain g and p
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

8. Finding Optimal Path Length
How many stages should we use to drive a given load?
1 stage?
2 stages?
3 stages?
4 stages?
[Harris, Sutherland]
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

9. Finding Optimal Path Length
Use LE to find delay.
Assume pinv = 1
f=64
1 stage
Td = 64 + pinv = 65
f=8
f=8
2 stages
Td = pinv = 18
f=4
f=4
f=4
3 stages
Td = pinv = 15
f=2.8
f=2.8
f=2.8
f=2.8
4 stages
Td = pinv = 15.2
[Harris, Sutherland]
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

10. Finding Optimal Path Length
Use LE to find delay.
Assume pinv = 1
f=8
f=8
2 stages
Td = pinv = 18
Best
f=4
f=4
f=4
3 stages
Td = 15
f=2.8
f=2.8
f=2.8
f=2.8
4 stages
Td = 15.2
Not far off…
[Harris, Sutherland]
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

11. A General Buffering Case
If we have a logic block and want to add inverters
Parasitic delay
of added inverters
Effort Delay
of path
Parasitic delay
of Logic Block
[Harris, Weste]
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

12. Prof. V. G. Oklobdzija: High-Performance System Design
A General Buffering Case
Minimize with respect to N
Assuming pinv = 0 yields the result F1/N =
With pinv = 1 yields the result F1/N = 3.59
[Harris, Weste]
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

13. Prof. V. G. Oklobdzija: High-Performance System Design
A General Buffering Case
1.51
1.26
1.15
(F1/N = 2.4)
(F1/N = 6)
0.7
Observation:
As long as F1/N is between 2.4 and 6 only 15% delay penalty
[Harris, Sutherland]
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

14. Prof. V. G. Oklobdzija: High-Performance System Design
Applying to General Design
We can use this as a starting point to estimate the optimal number of stages for a given design
All we have to do is determine F
Adder
Multiplier
F = GBH
F = GBH
= log3.59F
= log3.59F
But to determine F, we have to already know the design….
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

15. Prof. V. G. Oklobdzija: High-Performance System Design
Applying to General Design
If we already know the design, we might be able to
quantify the “goodness” of a design.
For example:
Adder
8 stages
F = GBH = 2150
= log3.59F = 6
But the adder has 8 stages (not 6)…
Problem is that if we change the adder to 6 stages, the types
of gates will change (G, P) and the branching (B) will change.
Useful for simple structures.
Difficult to apply to complex structures
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

16. Prof. V. G. Oklobdzija: High-Performance System Design
Applying to General Design
So far we’ve handled simple paths…
What about when we handle the entire design?
Branching seems like a headache now…
Does it get worse when we analyze the entire
design?
How do we handle:
- Multiple inputs
- Different path lengths
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

17. Handling Multiple Input Paths
Need to figure out how to size Path A, B and C…
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

18. Handling Multiple Input Paths
Same idea as branching, make the delay of each path equal
Td-A = Td-B = Td-C
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

19. Handling Multiple Input Paths
Path A and B have more branching than Path C…
- possibly different F
Equal delay could mean Input A ≠ Input B
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

20. Handling Multiple Input Paths
If all gates are inverters & H=32 C1 C2 C3
fA = (1*B*32)^(1/3) = 4.21
Td-A = pinv C4 C6 C5
fB = (1*B*32)^(1/3) = 4.21
Td-B = pinv
fC (GBH)^(1/3) = 3.5
Size using f=4.21, Cout = 32
Td-C = pinv
C3 = C6 = 7.6
C2 = 1.81
C5 = 2.41
C1 = 1
C4 = 0.5
Apply Logical Effort for each path (use same H for each)
Worst case delay determines worst case path
- Use that f to size every path
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

21. Handling Multiple Input Paths
Can size for optimal delay simply by applying the
same f to every gate in the design
As long as we determine sizing correctly, we can find worst case path by finding the largest input (defines H).
No need to do branching anymore…
(of course now we have to handle the entire circuit)
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

22. Handling Multiple Input Paths
Apply f = 3 C1 C2 C3
= 32 C4
= 32 C6 C5
C3 =
10.67
C6 =
10.67
C2 =
3.56
C5 =
4.74
C1 =
2.77
C4 =
1.58
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

23. Handling Multiple Input Paths
Apply f = 4 C1 C2 C3
= 32 C4
= 32 C6 C5
C3 = 8
C6 = 8
C2 = 2
C5 =
2.67
C1 =
1.17
C4 =
0.67
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

24. Handling Multiple Input Paths
Can size every gate in a regular structure.
From these sizings we can estimate energy
can include parasitic and gate capacitance
switching (if you want)
- HSPICE can be used to include crowbar and leakage
Problem…
- What about branches with different number of gates?
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

25. Prof. V. G. Oklobdzija: High-Performance System Design
Handling Different Path Lengths
What if branches have the different lengths?
1 gate
2 gates
Can LE still be applied?
- yes… but no easy way…
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

26. Prof. V. G. Oklobdzija: High-Performance System Design
Advanced Branching
1 gate
Difficult to ratio
C3 and C5… C5
Path B C1 C2 C4 C3
Path A
2 gates
For the optimal solution,
TA = TB
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

27. Prof. V. G. Oklobdzija: High-Performance System Design
Advanced Branching
1 gate C5
Path B C1 C2 C4 C3
Path A
2 gates
For Path B to have the same delay as Path A
- Delay of the branches should be equal.
f5 = f3 + f4
f1 = f2
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

28. Advanced Branching Solve for H=16 Path B Path A
1 gate
Solve for H=16
Note: Solution ignores
parasitics C5
Path B C1 C2 C4 C3
Path A
2 gates
Optimizing yields:
f4 = 2.06
f5 = 4.12
Hard to solve
Requires numerical
approach
f3 = 2.06
f2 = 2.76
Td = parasitics
f1 = 2.76
What if we apply the equal f approach?
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

29. Advanced Branching Solve for H=16 Path B Path A Solution Space
1 gate
Solve for H=16
Note: Solution ignores
parasitics C5
Path B C1 C2 C4 C3
Path A
2 gates
Forcing f’s to be equal on the critical path yields:
f4 = 2.44
f5 = 4.88
f3 = 2.44
Solution Space
Is relatively
Flat
f2 = 2.44
Td = parasitics
f1 = 2.44
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

30. Prof. V. G. Oklobdzija: High-Performance System Design
Advanced Branching (with Parasitics)
Solve for H=16
1 gate C5
Path B C1 C2 C4 C3
Path A
2 gates
Forcing f’s to be equal on the critical path yields:
Note: pinv = 1
f4 = 1.98
f5 = 4.96
f3 = 1.98
f5 = f4 + f3 + parasitic diff. =
= 4.96
f2 = 2.7
Td =
f1 = 2.7
Can handle parasitics difference if we want…
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

31. Prof. V. G. Oklobdzija: High-Performance System Design
Advanced Branching (with Parasitics)
1 gate
Solve for H=16 C5
Path B C1 C2 C4 C3
Path A
2 gates
Optimizing yields:
f4 = 2.37
f5 = 5.74
Note: pinv = 1
f3 = 2.37
f5 = f4 + f3 + parasitic diff. =
= 5.74
f2 = 2.37
Td =
f1 = 2.37
Can handle parasitics difference if we want…
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design

32. Prof. V. G. Oklobdzija: High-Performance System Design
Fall 2004
Prof. V. G. Oklobdzija: High-Performance System Design