1. DAC38RF84 Test

2. DAC38RF84 Test Test Setup: 100MHz complex tone sent from TSW14J56EVM
Ext 400MHz reference clock to J4.
Shunt on JP10 removed. Shunt on JP3 installed.
Test conditions:
Fdac = 6400Msps PLL mode
SYSREF = 26.66MHz.
12x Interpolation
DAC Input Data Rate = MHz, TSW14J56EVM Ref CLK = M
LMFS = 421
DAC PLL settings M = 4, N = 1
single DAC, 1 IQ

3. DAC GUI

4. DAC GUI

5. LMK Clock Output tab

6. SYSREF divider

7. Go to the Quick Start tab and click on “PLL AUTO TUNE” to lock the DAC PLL

8. Go to the DAC38RF8x tab then the Clocking tab and click on “Check Loop Filter Voltage”. The PLL LF Voltage box should report a number between 3-5 and the SERDES PLL0 and PLL1 Out of lock indicators should be off as shown below.

9. HSDC Pro setup. After parameters below are entered, click “Send”