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Joshua Beaudet & Michael Klempa

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Presentation on theme: "Joshua Beaudet & Michael Klempa"— Presentation transcript:

1 Joshua Beaudet & Michael Klempa
UNH-IOL SAS Test Tool Joshua Beaudet & Michael Klempa

2 Project Goals Create a tool using an FPGA for the UNH-IOL that connects to a SAS device Make it versatile for future testing

3 Practical Uses Testing a SAS drive or host’s state machines (SN, OOB, etc.) Golden Reference device

4 Design Inspiration

5 LeCroy Sierra M6-2 Advantages Disadvantages Established Software GUI
Analyzer built in Disadvantages Crashes frequently Returns false data

6 Virtex 6

7 Virtex 6 Advantages Disadvantages Speed capabilities Robustness
Versatility Abundant References Disadvantages Highly Complex infrastructure Fragile Unfamiliarity

8 Setup

9 Why VHDL? Robustness IEEE Standard Ubiquitous

10 SAS Referencing SAS 2.1 Rev. 7 Specification Serial Attached SCSI
Enterprise Level Storage Technology 8b/10b encoding, differential NRZ signaling Focus: Establishing Link between two devices

11 OOB Definition: Out of band (OOB) signals are low-speed signal patterns that do not appear in normal data streams. OOB signals consist of defined amounts of idle time followed by defined amounts of burst time

12 OOB State Machine

13 OOB Demo

14 COMINIT & COMSAS COMINIT begins the OOB sequence
COMSAS is used to show that the device is a SAS device

15 Speed Negotiation Goal: Find a commonly supported speed between two link partners Covers 6, 3, and 1.5G SAS Series of “Windows”

16 Speed Negotiation State Machine

17 Budget Item Cost Actual From Virtex 6 FPGA $5,000 $0 Xilinx SAS Drive
$300 UNH IOL

18 Project Schedule

19 Questions?


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