1. Improved Architecture of Logarithmic Converter by Digit-Recurrence with Selection by Rounding
Han Liu
Partner: Dongdong Chen
Supervisor: Seok-Bum Ko
Electrical & Computer Engineering Department Mar-30

2. Outline Background Introduction of Algorithm Previous Design
Improvements on Architecture
Comparison

3. Background Decimal Floating Point format: Logarithm of V is:
V=(-1)S×10E×Significand
Logarithm of V is:
R=log10(V)=log10(10E)+log10(Significand)
Since DFP is not a normalized number, then after normalizing significand to range [0.1, 1), then R is represented in,
R=E+k+log10(m)
Significand = m × 10k

4. Introduction of Algorithm (1/2)
log10(m) = log10(m∏fj)-∑log10(fj)
where lim{m∏fj} → 1,
then lim{log10(m∏fj)} → 0
thus log10(m) = 0 - ∑log10(fj)
(fj = 1+ej10-j)
E[j+1] = E[j] ×(1+ej10-j)
L[j+1] = L[j]-log10(1+ej10-j)
where E[1] = m, L[1] = 0

5. Introduction of Algorithm (1/2)
E[N+1] ≈ 1
L[N+1] ≈ log10(m)
W[j] = 10j(1-E[j])
so E[j] = 1-W[j]10-j
W[j+1] = 10(W[j]-ej+ejW[j]10-j)
where W[1] = 10(1-m’)
m : [0.1, 1)
m’ : [0.5, 1)

6. Previous Design

7. Improvements on Arch. (1/4)

8. Improvements on Arch. (2/4)

9. Improvements on Arch. (3/4)

10. Improvements on Arch. (4/4)

11. Comparison TSMC-180 nm ST-90 nm Previous design (32bit) 9.26 ns 5 ns
Improved design (64bit) NA
1.1 ns
Comparison on critical path

12. Question
Thanks!