1. CS501 Advanced Computer Architecture
Lecture08
Dr.Noor Muhammad Sheikh

2. Review

3. FALCON-A Instruction formats
Type I 15
Op-code
unused 11 10 15 11 10 8 7
Type II
Op-code ra c2 15 11 10 8 7 5 4
Type III
Op-code ra rb c1 15 11 10 8 7 5 4 2 1
Type IV
Op-code ra rb rc
unused

4. Encoding for the GPRs to be used in place of ra, rb, or rc
Registers
Code R0
000*** R1
001 R2
010 R3
011 R4
100 R5
101 R6
110 R7
111

5. Type I five instructions15
Op-code
unused 11 10
five instructions
nop (op-code = 21) may be useful in pipelining
reset (op-code = 30 )
halt (op-code = 31)
int (op-code = 26)
iret (op-code= 27)
All are 0-operand

6. Type II movi (op-code = 7 ) load register with a constantra 8 10 11 15 c2 7
movi (op-code = 7 ) load register with a constant
movi R3, 56 R[3] ← 56
in (op-code = 24) load register from input device
in R3, 57 R[3] ← IO[57]
out (op-code = 25) move from register to output device
out R7, 34 IO[34] ← R[7]
ret (op-code=23) return from subroutine using register
ret R3 PC ← R[3]

7. Type II jz (op-code= 19) jump if zerora 8 10 11 15 c2 7
jz (op-code= 19) jump if zero
jz r3, [4] (R[3]=0): PC← PC+ 4;
jnz (op-code= 18) jump if not zero
jnz r4, [variable] (R[4]≠0): PC← PC+ variable;
jpl (op-code= 16) jump if positive
jpl r3, [label] (R[3]≥0): PC ← PC+ (label-PC);
jmi (op-code= 17) jump if negative
jmi r7, [address] (R[7]<0): PC← PC+ address;

8. Type II jump (op-code= 20) unconditional jumpra 8 10 11 15 c2 7
1. Constant, Variable, address or (label – PC) should be in the range -128 to + 127
2. IF jump [r0+a] is used, it means jump [a]
3. jump [-r2] is not allowed by the assembler
4. Target address should always be EVEN
jump (op-code= 20) unconditional jump
Forms allowed by the assembler:
jump [ra + constant]
jump [ra + variable]
jump [ra + address]
jump [ra + label]
For all the above instructions:
(ra=0):PC← PC+(8αC2<7>)©C2<7..0>,
(ra≠0):PC← R[ra]+(8αC2<7>)©C2<7..0>;
C2 is computed by sign extending the constant, variable, address, or (label –PC)
Types of unconditional jumps possible:
Direct
Indirect
PC relative (near)
Register relative (far)

9. Type III andi (op-code = 9 ) and constant to register15 11 10 8 7 5 4
Op-code ra rb c1
andi (op-code = 9 ) and constant to register
andi r4, r3, 5 R[4] R[3] & 5
addi (op-code = 1 ) add constant to register
addi r4, r3,4 R[4] R[3] + 4
subi (op-code = 3 ) subtract constant from register
subi r5, r7, 9 R[5] R[7] - 9
ori (op-code= 11) or register with constant
ori r4, r7, 3 R[4] R[7] ~ 3

10. Type III shiftl r4, r3, 7 shiftr r4, r3,915 11 10 8 7 5 4
Op-code ra rb c1
shiftl (op-code = 12 ) shift register left
shiftl r4, r3, 7
shiftr (op-code = 13 ) shift register right
shiftr r4, r3,9
asr (op-code = 15 ) arithmetic shift right
asr r1, r2, 5
load (op-code= 29) load register from memory
load r1, [r4 +15] R[1] M[R[4]+15]
store (op-code= 28) store register to memory
store r6, [r7+13] M[R[7]+13] R[6]

11. Type III Modified mov (op-code = 6 ) register to registerra rb 4 5 7 8 10 11 15
unused
mov (op-code = 6 ) register to register
mov r4, r3 R[4] R[3]
not (op-code = 14 ) invert register
not r4, r R[4] !R[2]
call (op-code = 22 ) call subroutine
call r4, r3 R[4] PC, PC R[3]

12. Type IV add (op-code = 0 ) add register to registerra rb rc
unused 1 2 4 5 7 8 10 11 15
add (op-code = 0 ) add register to register
and r4, r3, r5 R[4] R[3] +R[5]
sub (op-code = 2 ) subtract reg from reg
sub r4, r3, r5 R[4] R[3] – R[5]
mul (op-code = 4 ) multiply
mul r5, r7, r1 R[0] © R[5] ← R[5]*R[1]
div (op-code= 5) divide
div r4, r7, r2 R[4]←R[0] ©R[7]/R[2],R[0]←R[0] ©R[7]%R[2]
and (op-code= 8) and register to register
and r1, r4, r5 R[1] R[4] & R[5]
or (op-code= 10) or register to register
or r6, r7,r2 R[6] R[7] ~ R[2]

13. FUNCTIONAL GROUPS OF INSTRUCTIONS
Control Instruction
Mnemonic
opcode
No operation
nop
(21)
call
(22)
return
ret
(23)
interrupt
int
(26)
Interrupt return
iret
(27)
reset
(30)
halt
(31)

14. FUNCTIONAL GROUPS OF INSTRUCTIONS
Data Transfer Instructions
Mnemonic
opcode
move
mov
(6)
Move immediate
movi
(7)
Input to register in
(24)
Output from register
out
(25)
Load from memory
load
(29)
Store into memory
store
(28)

15. FUNCTIONAL GROUPS OF INSTRUCTIONS
jump instruction
Mnemonic
opcode
jump if positive
jpl
(16)
jump if negative
jmi
(17)
jump if not zero
jnz
(18)
jump if zero jz
(19)
jump
(20)

16. FUNCTIONAL GROUPS OF INSTRUCTIONS
Arithmetic instruction
Mnemonic
opcode
Add
add
(0)
Add immediate
addi
(1)
Subtract
sub
(2)
Subtract immediate
subi
(3)
Multiply
mul
(4)
Divide
div
(5)

17. FUNCTIONAL GROUPS OF INSTRUCTIONS
Logic Instruction
Mnemonic
opcode
And
and
(8)
And immediate
andi
(9) Or or
(10)
Or immediate
ori
(11)
Shift left
shiftl
(12)
Shift right
shiftr
(13)
Not
not
(14)
Arithmetic shift right
asr
(15)

18. Example 1: Identify the types of following FALCON-A instructions and specify the values in the fields
Instruction
Type ra rb rc c1 c2
movi r1, 2
add r1,r2,r3
nop
load r2,[r5 + 6]
jz r0, [3]

19. Example 1: Identify the types of following FALCON-A instructions and specify the values in the fields
Instruction
Type ra rb rc c1 c2
movi r1, 2 II r1 - 2
add r1,r2,r3 IV r2 r3
nop I
load r2,[r5 + 6]
III r5 6
jz r0, [3] r0 3

20. Example 1: Identify the types of following FALCON-A instructions and specify the values in the fields
Instruction
Machine Code ra rb rc c1 c2
movi r1, 2
3902h r1 - 2
add r1,r2,r3
014Ch r2 r3
nop
A800h
load r2,[r5 + 6]
EAA6h r5 6
jz r0, [3]
9803h r0 3

21. Example 2: Identify the addressing modes and RTL description (meaning) for the following FALCON-A instructions
Instruction
Addressing mode
RTL description
(meaning)
load r2,[r4 + 8]
jnz r1,[54]
shiftl r1,r2,4
addi r3,r6,2
sub r1, r7,r2

22. Example 2: Identify the addressing modes and RTL description (meaning) for the following FALCON-A instructions
Instruction
Addressing mode
RTL description
(meaning)
load r2,[r4 + 8]
Displacement
R[2] M[R[4]+8]
jnz r1, [54]
Relative
(R[1]≠0):
PC PC+54
shiftl r1,r2,4
Immediate
Shift r2 left 4 times and store in r1
addi r3,r6,2
R[3] R[6]+2
sub r1, r7,r2
Register
R[1] R[7]-R[2]

23. Example 3: Specify the condition for the branch instruction and the status of the PC after the branch instruction executes with a true branch condition
Instruction
Condition
PC status
jz r2,[35]
jump [12]
jnz r6, [3]
jpl r1, [45]
jmi r2, [20]

24. Example 3: Specify the condition for the branch instruction and the status of the PC after the branch instruction executes with a true branch condition
Instruction
Condition
PC status
jz r2,[35]
If R[2]==0
PC PC+35
jump [12]
always
PC PC+12
jnz r6, [3]
If R[6] ≠ 0
PC PC+3
jpl r1, [45]
If R[1] ≥ 0
PC PC+45
jmi r2, [20]
If R[2] < 0
PC PC+20

25. Example 4: Specify the binary encoding of the different fields in the following FALCON-A instructions.
Instruction
TYPE
opcode ra rb rc
C1(5 bits) OR
C2(8 bits)
store r4, [r1+8]
sub r3,r6,r5
shiftr r4,r6,9
jump [10]
halt

26. Example 4: Specify the binary encoding of the different fields in the following FALCON-A instructions.
Instruction
TYPE
opcode ra rb rc
C1(5 bits) OR
C2(8 bits)
store r4, [r1+8]
III
11100
100
001 -
01000
sub r3,r6,r5 IV
00010
011
110
101
shiftr r4,r6,9
01101
01001
jump [10] II
10100
halt I
11111