1. Electronics for the PID
We convinced ourselves that the approaches to the 2 different PID subsystem (barrel and forward) electronics have to be different:
The reasons for such a philosophy are:
The number of channels ~ 1/ 100 ( barrel/forward )
The targeted performances in time resolution ~ 1/10 ( barrel/forward)
For the barrel we could follow a conservative solution. The available technology is ok. We need to perform some R&D but we are confident in the results. The requirements are pretty well defined.
For the forward there are many issues:
studies of the fast PMs
radiation level
detector implementation
time performance of the electronics.
Christophe Beigbeder
16 Juin 2009

2. Requirements for the Barrel electronics:
Number of channels :
~ in case of Focusing DIRC ( see PID // sessions for details )
~ in case on non Focusing DIRC (Babar-like with a smaller SOB)
Time resolution :
ps for the PM => ~100 ps for the electronics
Amplitude measurement
Focusing : 3 * 12 mm pixel with Hamamatsu H We may need to estimate the pulse height in order to correct the time measurement.
-> needs to be further studied : low walk discriminator.
Non Focusing : 6* 6 mm Hamamatsu H-8500
We may need the amplitude measurement for better spatial resolution
Our experience in the DIRC is that for understanding, testing and commissioning the detector, the amplitude measurement is very useful.
-> Need to design a analog chip
Christophe Beigbeder
16 Juin 2009

3. Time resolution for electronics : ~ 10 ps
The forward
Electronics requirements for the forward PID for the 3 options of the detector. ( Jerry’s talk this afternoon in mach intergration session )
DIRC-like TOF
Number of channels : 192
Pixelated TOF
Number of channels : 7200
Aerogel
Number of channels : ~15000
Time resolution for electronics : ~ 10 ps
Data rate per channel : 0,75 MHz / pixel (DIRC-like ) ~ 3KHz ( Pix TOF)
Very close to the beam pipe in both cases
-> radiation level is an issue
Christophe Beigbeder
16 Juin 2009

4. Possible implementation For the Barrel
A solution similar to Babar’s DFB could be proposed (TDC based)
Precision time measurement. Ongoing R&D on a reduced time walk Orsay.
TDC with 100 ps rms resolution. Test of the SNATS chip ( next slide )
Actel PGA for signal processing and DAQ interface.
The test of BLAB2 is still going on
For the Forward
Best solutions are based on analog memories
Test of Target chips by SLAC are very encouraging
The performance shown still have to be improved but the R&D is very active and the goal of reaching the 10 ps in a regular way looks accessible.
LAL analog memories will also be tested soon on the SLAC cosmic telescope
-> G.Warner and Dominique are working hard in this field
One of the main issues is the relatively low readout speed which may limit the trigger rate
Analog memories are powerful tools for characterization and study of PMs
They are ideally suited for fast electronics test benches
Their use in the case of many 10000’s channels however has to be carefully studied.
Potential dead-time due to readout
Especially if the number of samples needed for signal reconstruction is high.
This could be partly solved with an derandomizer internal to the analog memory and simultaneous write/read of the different banks.
Christophe Beigbeder
16 Juin 2009

5. SNATS : a chip for Absolute Time Measurement
Technology Process: AMS CMOS 0.35µm
Clock Frequency: 160MHz
Number of cells: 32 ( limited by the INL )
Dynamic Range: 53 bits
48 clock counter bits
5 interpolator bits
Time coverage: 20 days
LSB = 200ps
DNL ~ 10%
Channels per chip = 16
Dead time per channel : 400ns => 16 * 400 per 16 channels
Production : shared run as for Babar. 67 Euros / chip based on a recent production of ~ 500 chips.
Not “ naturally “ protected against SEL.
A 100 ps TDC can be developed based on this chip
Christophe Beigbeder
16 Juin 2009

6. Tests @ SLAC and next steps
A possible design for the barrel based on the SNATS, before preparing a specific version of the chip based on the same principles
Proposal for a 16 or 64 channel test board for mid 2010
Test of the performance of the Wave Catcher board based on the 12-bit/3.2 G/sec SAM chip in October during the next SuperB meeting.
Test of the Target chip still goes on.
Proposal for the integration of the PID electronics in ETD architecture will soon be presented.
Christophe Beigbeder
16 Juin 2009