1. Machine-Level Programming I: Basics Comp 21000: Introduction to Computer Organization & Systems
Instructor:
John Barr
* Modified slides from the book “Computer Systems: a Programmer’s Perspective”, Randy Bryant & David O’Hallaron, 2011

2. Today: Machine Programming I: Basics
History of Intel processors and architectures
C, assembly, machine code
Assembly Basics: Registers, operands, move
Intro to x86-64
Real programmers can write assembly code in any language.
-- Larry Wall, creator of the Perl language

3. Processors
What is a processor?
Computer brains

4. Intel x86 Processors Totally dominate laptop/desktop/server market
but not the phone/tablet market (that’s ARM)
Evolutionary design
Backwards compatible up until 8086, introduced in 1978
Added more features as time goes on
Complex instruction set computer (CISC)
Many different instructions with many different formats
But, only small subset encountered with Linux programs
Hard to match performance of Reduced Instruction Set Computers (RISC)
But, Intel has done just that!
In terms of speed. Less so for low power.

5. Intel x86 Evolution: Milestones
Name Date Transistors MHz
K 5-10
First 16-bit Intel processor. Basis for IBM PC & DOS
1MB address space
K 16-33
First 32 bit Intel processor , referred to as IA32
Added “flat addressing”, capable of running Unix
Pentium 4E M
First 64-bit Intel x86 processor, referred to as x86-64
Core M
First multi-core Intel processor
Core i M
Four cores

6. Intel x86 Processors, cont.
Machine Evolution M
Pentium M
Pentium/MMX M
PentiumPro M
Pentium III M
Pentium M
Core 2 Duo M
Core i M
Corie i B
Added Features
Instructions to support multimedia operations
Instructions to enable more efficient conditional operations
Transition from 32 bits to 64 bits
More cores

7. Intel x86 Processors: Overview
Architectures
Processors
X86-16
8086
286
X86-32/IA32
386
486
Pentium
Pentium MMX
Pentium III
Pentium 4
Pentium 4E
MMX
SSE
SSE2
SSE3
X86-64 / EM64t
Pentium 4F
Core 2 Duo
Core i7
time
SSE4
IA: often redefined as latest Intel architecture

8. 2015 State of the Art Desktop Model Server Model
Core i7 Skylake 2015 (6th generation)
Cannon Lake is 10nm version in 2018
Desktop Model
4 cores
Integrated HD graphics 530
14 pipeline stages
GHz
15W
Server Model
8 cores
Integrated I/O
2-2.6 GHz
65W

9. More Information
Intel processors (Wikipedia)
Intel microarchitectures

10. x86 Clones: Advanced Micro Devices (AMD)
Historically
AMD has followed just behind Intel
A little bit slower, a lot cheaper
Then
Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies
Built Opteron: tough competitor to Pentium 4
Developed x86-64, their own extension to 64 bits
Recent Years
Intel got its act together
Leads the world in semiconductor technology
AMD has fallen behind
Relies on external semiconductor manufacturer

11. Intel’s 64-Bit History
2001: Intel Attempts Radical Shift from IA32 to IA64
Totally different architecture (Itanium)
Executes IA32 code only as legacy
Performance disappointing
2003: AMD Steps in with Evolutionary Solution
x86-64 (now called “AMD64”)
Intel Felt Obligated to Focus on IA64
Hard to admit mistake or that AMD is better
2004: Intel Announces EM64T extension to IA32
Extended Memory 64-bit Technology
Almost identical to x86-64!
All but low-end x86 processors support x86-64
But, lots of code still runs in 32-bit mode

12. Our Coverage IA32 x86-64/EM64T Presentation The traditional x86
The standard
server> gcc hello.c
server> gcc –march=x86-64 hello.c
Presentation
Book covers x86-64
Web aside on IA32
We will only cover x86-64
This forces the compiler to produce 64-bit code on a 32-bit machine

13. Today: Machine Programming I: Basics
History of Intel processors and architectures
C, assembly, machine code
Assembly Basics: Registers, operands, move
Intro to x86-64

14. Definitions
Architecture: (also ISA: instruction set architecture) The parts of a processor design that one needs to understand or write assembly/machine code.
Examples: instruction set specification, registers.
Microarchitecture: Implementation of the architecture.
Examples: cache sizes and core frequency.
Code Forms:
Machine Code: The byte-level programs that a processor executes
Assembly Code: A text representation of machine code
Example ISAs:
Intel: x86, IA32, Itanium, x86-64
ARM: Used in almost all mobile phones

15. Assembly Programmer’s View
Memory
CPU
Addresses
Registers
Object Code
Program Data
OS Data PC
Data
Condition
Codes
Instructions
Stack
Programmer-Visible State
PC: Program counter
Address of next instruction
“RIP” (x86-64)
Register file
Heavily used program data
Condition codes
Store status information about most recent arithmetic operation
Used for conditional branching
Memory
Byte addressable array
Code, user data
Stack to support procedures

16. Program’s View: memory
invisible to
user code
Kernel virtual memory
0xC
User stack
(created at runtime)
%esp (stack pointer)
Variables in functions go here
Memory mapped region for
shared libraries 0x
NOTE: MEMORY GROWS UP; 0 IS AT BOTTOM!
brk
Variables in main() go here
Run-time heap
(created at runtime by malloc)
Read/write segment
(.data, .bss)
Loaded from the
executable file
Machine instructions and constants go here
Read0nly segment
(.init, .text, .rodata) 0x
Unused
.data = global and static variables; .bss = global variables initialized to 0; .text = code; .rodata = constants (read only)

17. CPU’s View: fetch, decode, execute
Kernel virtual memory
Memory
invisible to
user code
CPU
0xc
User stack
(created at runtime)
Registers R I P
%esp (stack pointer)
Condition
Codes
Memory mapped region for
shared libraries 0x
brk
Run-time heap
(created at runtime by malloc)
Read/write segment
(.data, .bss)
Fetch instruction from memory (%rip contains the address in memory)
Increment %rip to next instruction address
Loaded from the
executable file
Read-only segment
(.init, .text, .rodata) 0x
Unused

18. CPU’s View CPU Registers R I P Condition Codes Memory invisible to
user code
Kernel virtual memory
CPU
0xc
User stack
(created at runtime)
Registers R I P
%esp (stack pointer)
Condition
Codes
Memory mapped region for
shared libraries 0x
brk
Run-time heap
(created at runtime by malloc)
2. Decode instruction and fetch arguments from memory (if necessary)
Operand could come from R/W segment, heap or user stack
Read/write segment
(.data, .bss)
Loaded from the
executable file
Read-only segment
(.init, .text, .rodata) 0x
Unused

19. CPU’s View CPU Registers R I P Condition Codes Memory invisible to
user code
Kernel virtual memory
CPU
0xc
User stack
(created at runtime)
Registers R I P
%esp (stack pointer)
Condition
Codes
Memory mapped region for
shared libraries 0x
brk
Run-time heap
(created at runtime by malloc)
3. Execute instruction and store results
Operand could go to R/W segment, heap or user stack
Read/write segment
(.data, .bss)
Loaded from the
executable file
Read-only segment
(.init, .text, .rodata) 0x
Unused

20. CPU’s View CPU Registers R I P Condition Codes Memory invisible to
user code
Kernel virtual memory
CPU
0xc
User stack
(created at runtime)
Registers R I P
%esp (stack pointer)
Condition
Codes
Memory mapped region for
shared libraries 0x
brk
Run-time heap
(created at runtime by malloc)
Read/write segment
(.data, .bss)
1. Repeat: Fetch next instruction from memory (%rip contains the addess in memory)
Loaded from the
executable file
Read-only segment
(.init, .text, .rodata) 0x
Unused

21. Example
See:
Much simpler than the IA32 architecture.
Does not make the register file explicit.
Uses an accumulator (not in IA32).