1. Data Collection Module (DCM) (review, fabrication plan & chain test)
DCM team
Cheng-Yi Chi ( DCM, TOF FEE, BB FEE)
Jamie Nagle (DCM)
Bill Sippach (DCM, TOF FEE, BB FEE)
Herb Cunitz (DCM, TOF FEE, BB FEE)
Li Zhang (DCM, TOF FEE, BB FEE)
June 10, 98 FEE Review
Cheng-Yi Chi

2. DCM Functions Zero-suppress FEM data
Receive Level-1 trigger primitives
Apply calibration constants
Error and alignment checking / handling
Re-format data to the Event Builder
Data Monitoring / Histogramming / Calibration
First Stage of the event building
Generating higher level trigger primitives
Provide FEM data buffer
June 10, 98 FEE Review
Cheng-Yi Chi

3. DCM Block Diagram
June 10, 98 FEE Review
Cheng-Yi Chi

4. DCM Crate
June 10, 98 FEE Review
Cheng-Yi Chi

5. Data Collection Module (DCM)
VME64X Backplane
Zero-Suppression
Daughter Card
LVL-1 Input
Fiber Connection
SHARC DSP
C.Y. Chi, J.L. Nagle
Columbia University
Data Flow through DCM
June 10, 98 FEE Review
Cheng-Yi Chi

6. Data Collection Module
Heat Transfer Plate
VME
64X
Handler
SHARC
DSP
Zero Suppression Daughter card
June 10, 98 FEE Review
Cheng-Yi Chi

7. includes VME block read buffer
Partitioner
Data flow control FPGA
includes VME block read buffer
ALTERA EPF10K40
FIFO’s
Event Data flow
To sub-event
buffer
Busy
From L1
L1 Primitives
June 10, 98 FEE Review
Cheng-Yi Chi

8. DCM Final Design Review
Final design Review (Jan )
(John Haggerty, Glenn Young, Chris Witzig, Paul Stankus, Edmond Desmond, Seymour Rankowitz)
Important actions from FDR
additional few pull-down resistors added on to token-passing timing/control lines on DCM (fixed problems for the first modules in the token chain)
5th DSP on the DCM module will be 4 Mbits version of SHARC DSP, instead of 2 Mbits version (as requested by DCM team)
June 10, 98 FEE Review
Cheng-Yi Chi

9. Timing-FEM-DCM chain test
February 1998 TOF - DCM chain test (in Nevis)
April 1998 GTM-DC FEM-DCM
GTM-PC FEM-DCM Chain Test.
(~ 2 Days effort)
Julia Velkovska, Tom Hemmick, Chuck Pancake (Stony Brook),
Jamie Nagle (Nevis)
Joe Mead, Simon Durant (BNL) (Timing, ONCS)
Melissa Smith (ORNL)
Problems Found
DCM daughter card, Diode direction was reversed (frequency lock)
On GTM, reset had to be put in for initial GLINK fill frame transmission
June 10, 98 FEE Review
Cheng-Yi Chi

10. DCM Status DCM compressor daughter cards are done
DCM main board is done (waiting for chain test with Partitioner card & backplane)
DCM Partitioner card testing is 80% done
Remaining goal is a chain test between the sub-event buffer and Partitioner
June 10, 98 FEE Review
Cheng-Yi Chi

11. DCM Fabrication Plan
Parts Order started at End of March. 90% of parts on hand now (including all DSP’s & Optical Transceivers)
Fabricating compressor daughter card PC boards
P.O. for daughter card assembler placed
Start DCM main board fabrication process later this month
We have two complete test stands at Nevis
Third one will be placed in PHENIX counting house ASAP
Project completion date before End of Year
June 10, 98 FEE Review
Cheng-Yi Chi