1. L25 – Final Review AU 15 Final Exam – Classroom – Journalism 300
(in class)
Wednesday Dec 14th – 2:00pm-3:45pm

2. Copyright 2012 - Joanne DeGroat, ECE, OSU
Topics
In class exam
There may be a question on the traditional manual sequential machine methodology. This most likely would be to work out the state diagram of some sequence detector or straightforward state machine.
Much like the midterm.
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

3. Copyright 2012 - Joanne DeGroat, ECE, OSU
The course listing
Design and analysis of sequential circuits; digital circuit design using building blocks, programmable logic devices; design of basic computer components such as arithmetic logic units
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

4. Spring 15 topic on the exam
Besides state diagram knowledge and possible question.
Questions on the MicroBaby architecture.
Questions on the MicroBaby datapath and ALU.
Questions on the operation of MicroBaby
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

5. Copyright 2012 - Joanne DeGroat, ECE, OSU
HDL topics
The VHDL Entity
The VHDL Architecture
Writing the VHDL description of a small leaf unit to perform a specified function.
Writing a VHDL structural description to integrate several leaf units.
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

6. Copyright 2012 - Joanne DeGroat, ECE, OSU
HDL questions
Given a small leaf block specification write the ENTITY and ARCHITECTURE for it.
Probably a dataflow requiring one or two logic equations implemented as a concurrent signal assignment statement.
Given the ENTITY and ARCHITECTURE name create a structural architecture given a simple diagram.
Know how to select bits from a bit_vector, i.e.,
Having myvec : bit_vector (7 downto 0);
select the 4th bit -- myvec(4)
Select the 2nd bit – myvec(2)
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

7. Copyright 2012 - Joanne DeGroat, ECE, OSU
More HDL
Know the HDL way to specify state machines
An ARCHITECTURE with 3 process
The F/F process that latches next_state into state
The next_state PROCESS that given a current state and the value of inputs, generates a value for next_state.
The output PROCESS that generates the final outputs.
For a Moore machine this could be as simple as
valout <= cur_state;
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

8. Copyright 2012 - Joanne DeGroat, ECE, OSU
Almost certainly
Diagram of a sequential machine such as
Given a sequential machine diagram
What are next state equations?
Construct State Table
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

9. Copyright 2012 - Joanne DeGroat, ECE, OSU
Problem continued
Now having state table
Create the VHDL description with its 3 processes
Know if this a Mealy or Moore machine
Be able to create the VHDL if the VHDL coding is with symbolic notation for state, or a binary encoding of state.
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

10. Copyright 2012 - Joanne DeGroat, ECE, OSU
VHDL
Know the basic of ENTITIES and ARCHITECTURES, component use, declarative regions, scope.
You should be able to do leaf unit ENTITY and ARCHITECTURE coding.
You should be also to create structural VHDL designs.
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU