1. Closed Session
CMOS Circuit Development Update Investigators: C.K. Ken Yang Dejan Markovic Students: A. Amin, R. Dorrance, P. Mulage, Y. Toriyama

2. CMOS Schedule at a Glance
We are targeting testing in Q4 and tapeout of new design in Q5
6/9/09
today
6/21/10 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
MTJ1
Test
MTJ2
Test
MTJ3
Test
MTJ4
Test
MTJ5
Test
MTJ6
Test
CMOS run A
(90nm)
MTJ3
Test
Test
CMOS run B
(65/90nm)
MTJ5
Test
Test
CMOS run C
(65nm)
MTJ6
Test
Test
6/9/09
12/9/09
6/9/10
12/9/10
6/9/10
CMOS
tapeout

3. Progress of Task Complete First Test Chip
Final Design
Testing Features
Intel Design Review
Verilog Model with Temperature
Begin Second Test Chip
Design Margin/Sensitivity Analysis
65nm Technology

4. Test Chip Block Diagram and Layout
Red: Test features

5. STT-RAM Cell Reference SRAM cell Two STTRAM cells:
12F x 5.25F = 63 F2
Two-finger access devices with shared junction
Two STTRAM cells:
#1 Cell size = 5.5F  5F = 27.5 F2
#2 Cell size = 10.5F  5F = 52.5 F2
Meets Phase 1 target of 30 F2
27.5 F2
52.5 F2

6. Testability Features M5 is programming layer for MTJ or no MTJ
Dummy resistances can be connected on M5 to act as MTJ
External access to each bit-line
Direct MTJ+circuit resistance measurement
Reference resistance is programmable
In-situ extraction of MTJ resistance
Discussed potential for additional testing features during design review with Intel 12/15/2009

7. Simulated Read Access Time
Read delay between 1.5-3ns
Meets design metric
MTJ parameters
RMTJ = 500Ω  330Ω, TMR ~ 50%
3ns
1.5ns

8. Enhanced Compact Model
Verilog-A
Macro-spin model implements LLG equation with STT
13 device-specific parameters used for fitting model
Steady-state behavior
Accurate to within ±3%

9. Temperature Effects Verilog-A Transient behavior
7 of 13 parameters used for modeling temperature effects
Transient behavior
Evaluated against detailed micromagnetic simulations
Model tracks switching delay across temperature

10. STT Design Margin Analysis
Feasible region of MTJ devices depends on:
CMOS transistor performance, Access transistor size, Variations

11. Analysis of Feasibility Region
Compare technologies
Same width (2.5um), IWR (0.5mA) and parameter variation
Can be used to estimate yield and MTJ design requirements
New device
TMR2
TMR2
IBM-90nm-CMOS
VWL = VDD = 1 V
IWR = 500 μA
WA=2.54 μm
WP,MUX=16 μm
WN,MUX=8 μm
MOS-K varies +/- 20%
MOS-VT varies +/- 50mV
Current Sensing: VR= 600 mV
Current Sensing: ΔIR= 20 μA
IBM-65nm-CMOS
TMR1
TMR1

12. 65nm Design Goals and Specifications
Support I-STT and C-STT cells
From discussion with modeling/simulation/device groups
Short write pulses
0.2ns to 2ns of ~1mA or less
Bipolar write pulses
Improved cell density
Limited by access device size and write current
Explore possibility of shrinking cell size
Improved testability
Test pattern generation
Measurable yield

13. Current Effort IBM 65nm library installed
Pursuing the pad library
Target 10SF for high drive current
Exploring design space in 65nm
Exploring circuit design options for short large-amplitude bipolar pulses
Continue discussion with device group on desired circuit specifications
Exploring memory architecture and cell structures

14. Extras

15. MTJ Feasible Region IBM-90nm-CMOS VWL = VDD = 1 V IWR = 500 μA
WA=2.54 μm
WP,MUX=16 μm
WN,MUX=8 μm
MOS-K varies +/- 20%
MOS-VT varies +/- 50mV
MTJ: RA = 2 Ω.μm2
MTJ: KRA = 34 Ω.μm2/nm
MTJ: TMR = 100%
MTJ: KTMR = 200 %/nm
MTJ: ΔtMgO = 0.2 Ao
Current Sensing: VR= 600 mV
Current Sensing: ΔIR= 20 μA

16. STT-RAM Cell Design Space