1. Mr. Pradeep J NATIONAL INSTITUTE OF TECHNOLOGY,
(STB99061)
NATIONAL INSTITUTE OF TECHNOLOGY,
TIRUCHIRAPPALLI –
3-DAY TUTORIAL ON VERILOG HDL
Organized by
IEEE STUDENT BRANCH NIT TRICHY
Mr. Pradeep J
M.Tech Scholar NIT-T
Department of Electronics and Communication Engineering
22 March 2019

2. Today’s Topic
Module Instantiation
FSM

3. MODULE INSTANTIATION
A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface.
The process of creating objects from a module template is called instantiation, and the objects are called instances

4. 4 BIT ADDER

5. module half_adder(in_a,in_b,sum,carry);
input in_a,in_b;
output sum,carry;
assign sum = in_a ^ in_b;
assign carry = in_a & in_b;
endmodule
module full_adder (in_a,in_b,carryin,sum,carryout);
input in_a,in_b,carryin;
output sum,carryout;
wire sum1,carry1,carry2;
half_adder h1(in_a,in_b,sum1,carry1);
half_adder h2(sum1,carryin,sum,carry2);
assign carryout = carry1 | carry2;
module half_adder(in_a,in_b,sum,carry);
input in_a,in_b;
output sum,carry;
assign sum = in_a ^ in_b;
assign carry = in_a & in_b;
endmodule
module full_adder (in_a,in_b,carryin,sum,carryout);
input in_a,in_b,carryin;
output sum,carryout;
wire sum1,carry1,carry2;
half_adder h1(in_a,in_b,sum1,carry1);
half_adder h2(sum1,carryin,sum,carry2);
assign carryout = carry1 | carry2;
module adder4bit(a,b,sum,carryin,carryout);
input [3:0]a,b;
input carry;
output [3:0]sum;
output carryout;
wire [2:0]carry;
full_adder f1(a[0],b[0],carryin,sum[0],carry[0]);
full_adder f2(a[1],b[1],carry[0],sum[1],carry[1]);
full_adder f3(a[2],b[2],carry[1],sum[2],carry[2]);
full_adder f4(a[3],b[3],carry[2],sum[3],carryout);
Endmodule

6. module adder_test;
wire [3:0]sum;
wire carryout;
reg [3:0]a,b;
reg carryin;
adder4bit a1(a,b,sum,carryin,carryout);
initial
begin
#10 a=4'b1010;b=4'b1101;carryin=1'b1;
#10 a=4'b1110;b=4'b1001;carryin=1'b0;
end
$monitor($time,"%b %b %b %b %b",a,b,carryin,sum,carryout);
#100 $stop;
endmodule

7. INTRODUCTION TO FSM Combinational and Sequential Circuits
In a combinational circuit, the outputs depend only on the applied input values and not on the past history.
In a sequential circuit, the outputs depend not only on the applied input values but also on the internal state.
The internal states also change with time.
The number of states is finite, and hence a sequential circuit is also referred to as a Finite State Machine (FSM).
Most of the practical circuits are sequential in nature.

8. FSM

9. MEALY AND MOORE MACHINE

10. EXAMPLE 1

11.
begin
case(state)
s0: color = red;
s1: color = green;
s2: color = yellow;
endcase
end
endmodule
module light(clk,reset,color);
input clk,reset;
output reg [1:0]color;
parameter s0=2'b00,s1=2'b01,s1=2'b10;
parameter red = 2'b00, green =2'b01, yellow =2'b10;
reg [1:0]state;
clk)
begin
if (reset == 1'b1)
state <= s0;
else
case(state)
s0: state <= s1;
s1: state <= s2;
s2: state <= s0;
endcase
end

12. module light_test;
wire color;
reg clk,reset;
light l1(clk,reset,color);
initial
begin
reset = 1'b0;
clk = 1'b0;
end
always
#5 clk = ~clk;
#3 reset =1'b1;
#10 reset = 1'b0;
endmodule

13. EXAMPLE 2

14. module parity_gen(x,clk,reset,z)
input x,clk,reset;
output reg z;
parameter even =1'b0, odd = 1'b1;
reg state;
clk)
begin
if (reset ==1'b1)
state <= even;
else
case(state)
even: begin if(x == 1'b1)
state <= odd;
end
odd: begin if(x == 1'b1)
state <= even;
else
state <= odd;
end
endcase
begin
case(state)
even: z=1;
odd: z=0;
endmodule

15. module paritygentest;
wire z;
reg x,reset,clk;
parity_gen p1(x,clk,reset,z);
initial
begin
reset = 1'b0;
clk = 1'b0;
x=1'b0;
end
always
#5 clk = ~clk;
initial
begin
#3 reset =1'b1;
#10 reset = 1'b0;x=1'b1;
#10 x=1'b0;
#10 x=1'b1;
end
endmodule

16. EXAMPLE 3

17. SEQUENCE DETECTOR

18. always@(present_state,x)
begin
case(present_state)
s0: begin if(x==0) begin next_state = s1; z=0; end
else begin next_state = s0; z=0; end
end
s1: begin if(x==1) begin next_state = s2;z=0; end
else begin next_state = s1; z=0; end
s2: begin if(x==1) begin next_state = s3;z=0; end
else begin next_state = s1;z=0; end
s3: begin if(x==1) begin next_state = s0; z=0; end
else begin next_state = s1; z=1; end
endcase
endmodule
module sequence_detect(x,clk,reset,z);
input x,clk,reset;
output reg z;
parameter s0=2'b00,s1=2'b01,s2=2'b10,s3=2'b11;
reg [1:0]present_state,next_state;
clk)
begin
if(reset ==1)
preset_state <= s0;
else
present_state <= next_state;
end

19. module seq_detect_test;
wire z;
reg x,reset,clk;
sequence_detect(x,clk,reset,z);
initial
begin
clk=1'b0;
reset=1'b0;
x=1'b0;
end
always
#5 clk=~clk;
initial
begin
#3 reset = 1'b1;
#10 reset = 1'b0;
#10 x = 1'b0;
#10 x = 1'b1;
end
$monitor($time,"%b%b%b%b",x,clk,reset,z);
#100 $stop;
endmodule

20. A<=B B=1 A=0
C<=A

21. THANK YOU