1. EMBEDDED SYSTEMS
Prof. Ch.Ramesh
Embedded Systems 1

2. INTRODUCTION
Embedded system technology over view design challenges Processor Technology IC Technology design Technology Trade-offs.
Single purpose processors: RT, Level combinational logic, sequential logic( RT level), Custom single purpose processor design (RT Level), optimizing custom single processors.
General purpose processor : Basic architecture, pipelining, programmers view, development environment, ASIPS, microcontrollers and DSPs.
Prof. Ch.Ramesh
Embedded Systems 2

3. Embedded system over view Design challenges Processor Technology
IC Technology
Design Technology
Trade-offs.
Prof. Ch.Ramesh
Embedded Systems 3

4. Computer system consists of A micro processor
A system is a way of working , organizing, or doing one or many tasks according to a fixed plan, program, or set of rules.
A system can also an arrangement in which all its units assemble and work together according to the plan or program.
Eg:
Computer system consists of
A micro processor
A large memory comprising of
a. Primary memory (RAM, ROM, and fast accessible caches.)
b. Secondary memory (magnetic memory, tapes, and optical memory)
Input output
Networking units.
Prof. Ch.Ramesh
Embedded Systems 4

5. Embedded /real System :
An embedded system is the one that has a computer hardware with software embedded in it as one of its most important component to operate in real time is called real time system.
An embedded system has soft ware designed to keep in view of the three constraints:
Available system memory
Available processor speed
Need to limit power dissipation when running the system continuously. in cycles of wait run stop wakeup events.
Prof. Ch.Ramesh
Embedded Systems 5

6. Examples of Embedded Systems:
Antenna
camera
Cell phone
Aero space communication
Mobile computing b. Banking c. Defense d. Automobile
e. Networking systems f. Digital Cameras g. High Definition TVs
h. Robotics in Assembly
Note:
The embedded systems are scattered into so many areas. Hence it is used in small applications like home appliances to a very sophisticated applications
Prof. Ch.Ramesh
Embedded Systems 6

7. Characteristics of Embedded/Real Time Systems: 1. Single functioned
2. Tightly constrained
3. Reactive and real time
Prof. Ch.Ramesh
Embedded Systems 7

8. Single functioned:
An embedded system usually executes a specific program repeatedly
Case 1:
a desk top computer executes a variety of programs like spread sheets, word processors and video games etc.. The embedded system program is updated with a new version.
Case 2:
Several programs are swapped in and swapped out of a system due to size limitations.
Example: missile run one program cruise mode then load a second program form locking onto a target.
All the above exceptions represent a specific function.
Prof. Ch.Ramesh
Embedded Systems 8

9. Embedded systems can be of
Tightly Constrained:
All computing systems have constraints on design metrics, but those on the embedded systems can be especially tight.
The design metric is a measure of an implementation features such as cost ,size ,performance and power.
Embedded systems can be of
Low cost, size fit into single chip they are fast enough to meet the requirements and must consume less power.
To extend battery life and prevent the necessity of cooling fan.
Prof. Ch.Ramesh
Embedded Systems 9

10. REACTIVE AND REAL TIME:
Many embedded systems must continuously react to changes in the systems environment and must compute certain results in real time without delay.
Eg: cars cruise controller continually monitors and reacts to speed and break sensors.
It must compute acceleration and deceleration repeatedly with out delay or in a limited time.
Prof. Ch.Ramesh
Embedded Systems 10

11. CLASSIFICATION OF EMBEDDED / real time SYSTEMS
Small scale systems
Medium scale system
Sophisticated systems
Prof. Ch.Ramesh
Embedded Systems 11

12. Small scale embedded systems:
The systems are designed with a single 8 or 16 bit microcontrollers they have little hardware and software complexities.
The main programming tools for small scale embedded systems are editor, cross assembler specific to a microcontroller.
The software has to fit within the memory available and keep in view the need to limit the power dissipation when system is running continuously.
Prof. Ch.Ramesh
Embedded Systems 12

13. Medium scale embedded system:
These are designed with a single or few bit microcontrollers or DSPs are RISCs.
They have both software and hardware complexities.
The sources of programming for medium scale Embedded systems are RTOS, Source coding tools, simulator, debugger and Integrated Development Environment,
These systems may also employ the readily available ASSP ( Application Specific System Programming) and IP for various functions.
Prof. Ch.Ramesh
Embedded Systems 13

14. Sophisticated Embedded systems
1. Sophisticated Embedded systems have enormous hardware and software complexities and may need scalable processors or configurable processors and programmable logic arrays.
2. They are used in cutting edge applications that need hardware and software co design and integration in the final system.
3. TCP/IP Protocols stacking and network driver functions are implemented in the hardware to obtain additional sppeds by saving time.
Prof. Ch.Ramesh
Embedded Systems 14

15. Design Challenges 5. Flexibility
The embedded systems designer must construct an implementation that fulfills desired functionality. The following are the design metrics of Embedded Systems
5. Flexibility
6. Time to market
7. Maintainability
8. Safety
NRE Cost ( Nonrecurring engineering Cost)
Unit Cost
Size
Performance
Prof. Ch.Ramesh
Embedded Systems 15

16. Metrics: Improving the metrics of one will worsening the another. Eg:
Size reduction
Adapting to new technologies 3.
Familiarization with new HW and SW
If we reduce the an implementation size the implementation performance may suffer.
To meet this optimization challenges the designer must be comfortable with a variety of hard ware and software implementation technologies.
The designer must be able to migrate from one technology to another Technology in order to find the best implementation.
Prof. Ch.Ramesh
Embedded Systems 16

17. Time to market design metric:
Time to market constraint has become especially demanding in recent years.
The above figure shows the simple market window
The product would have highest sales
Further if we look in to window there is a loss of sales.
Revenues ( $)
Time in months
Prof. Ch.Ramesh
Embedded Systems 17

18. Loss of revenue can occur due to a delayed entry of product.
Peak revenue
Market rise
Peak revenue from
delayed entry
On time
Delayed
Market
Fall 2W A W
Time D
On time entry
Delayed Entry
Loss of revenue can occur due to a delayed entry of product.
Adding the difficulty of meeting the time to market constituent
Prof. Ch.Ramesh
Embedded Systems 18

19. NRE ( Non Recurring Engineering Cost) and unit cost design metrics
Assume there are three technologies
Technology one
Technology Two
Technology Three
NRE cost $2000
NRE Cost $30,000
NRE Cost $100,000
Unit cost = $100
Unit cost = $30
Unit cost = $2
$200,000
$200
$160,000
$160
Total Cost
$120,000
Per product Cost
$120
$80,000
$80
$40,000
$40
800
1600
2400
800
1600
2400
Number of units (volume)
Number of units (volume)
Prof. Ch.Ramesh
Embedded Systems 19

20. The same is illustrated with a graph.
By ignoring all other choice of metrics the best technology choice will depend on the number of units that are planned to produce.
The same is illustrated with a graph.
Total cost = NRE Cost + unit cost * # of units.
The cost per product is also calculated.
Performance design metrics:
Performance of a system is a measure of how the system takes to execute our desired tasks.
The measure of performance depends on the following:
1. Latency or response time
2. Throughput
Latency :The time between the start of the task execution and the end.
Throughput: the number of tasks that can be produced per unit time
The common method of comparing is to spedup of two systems
Prof. Ch.Ramesh
Embedded Systems 20

21. PROCESSOR TECHNOLOGY General purpose processors - software:
Processor technology relates to the architecture of the computation engine used to implement a system desired functionality.
General purpose processors and software
Single purpose processor and hardware
Application specific processors
General purpose processors - software:
It is a programmable device suitable for a variety of applications to maximize the number of devices sold.
1. Program memory
2. General data path
3. General purpose ALU
An embedded system designer simply uses a general purpose processor by programming the processor memory to carry out the required functionality.`
Prof. Ch.Ramesh
Embedded Systems 21

22. Single purpose processors:
A single purpose processor ia a digital circuit designed to execute exactly one program.
The embedded system designer must create a single purpose processor bny designing custom digital circuit.
Another common terms include are : coprocessor , accelerator, peripheral
Single purpose processors benefits:
1. Performance is fast
2. Size and power is small
3. Unit cost is low
4. Performance may not match with general purpose processors
The architectures of different processors are given below.
Prof. Ch.Ramesh
Embedded Systems 22

23. c b a General Purpose processor Controller Data path Data Memory
Application specific processor
Single Purpose processor
Controller
Control
logic
and
state
registers IR PC
Program Memory
Assembly Code
Total = 0
For I = 1 to ---
Register File
General ALU
Data path
Data Memory
Controller
Control
logic
and
state
registers IR PC
Program Memory
Assembly Code
Total = 0
For I = 1 to ---
Registers
CustomALU
Data path
Data Memory
Controller
Data path
Control
logic
Index
Total
state
registers +
Data Memory c b a
Prof. Ch.Ramesh
Embedded Systems 23

24. Application specific Processors:
It is a programmable processor optimized for a particular class of applications having common characteristics such as embedded control, digital signal processing, telecommunication applications.
The designer of the processor can optimize the data path for the application class.
ASIP is an embedded system that can provide the benefit of flexibility while achieving good performance.
Examples are microcontrollers, digital signal processors etc.
Embedded Systems 24

25. IC Technology Full custom VLSI
Semi custom ASIC ( Gate Array and Standard Cell)
PLD
Prof. Ch.Ramesh
Embedded Systems 25

26. DESIGN TECHNOLOGY System specification Behavioral specification
Design technology invloves in which we convert our concept of desired system functionality to an implementation.
We must not only design the implementation to optimize design metrics but we must do so quickly.
The design process involves top down design process . The designer refines the system through several abstraction levels
The designer go through the following
System specification
Behavioral specification
Register transfer specification
Logic specification
Prof. Ch.Ramesh
Embedded Systems 26

27. System specification :
The designer describes the desired functionality in some language. Often in natural language or preferably in executable language is known as system specification
Behavioral specification:
The designer refines this specifications and by distributing portions of programs among general or single purpose processors is known as behavioral Specifications for each processor.
Prof. Ch.Ramesh
Embedded Systems 27

28. RT specifications:
Converting the behavior on general purpose processors to assembly code and by converting the behavior on single purpose processor to a connection of register transfer components and state machines.
Logic specification:
The designer refines the register transfer level specifications of a single purpose processors into a logic specification consisting of Boolean equations.
Prof. Ch.Ramesh
Embedded Systems 28

29. Compilation synthesis Model simulators / Checkers
Automates exploration of implementation details for lower level
Libraries / IP : incorporates pre designed implementation from lower abstraction level into higher level
Test / Verification : Ensures correct functionality at each level thus reducing costly iterations between levels.
Compilation synthesis
Libraries / IP
Test/ Verification
System synthesis
HW / SW / OS
Model simulators / Checkers
Behavior
cross
HW – SW co simulators
RT Synthesis
RT Components
HDL simulators
Logic Synthesis
Gates / Cells
Gate Simulators
System
Specification
behavioral RT
Logic
To final implementation
Prof. Ch.Ramesh
Embedded Systems 29

30. The various approaches to improve the process for increased productivity. Each approach can be applied at any of the four abstraction levels they are
COMPILATION/ SYNTHESIS
LIBRARIES/ IP
TEST/ VERIFICATION
MORE PRODUCTIVITY IMPROVERS
Prof. Ch.Ramesh
Embedded Systems 30

31. Prof. Ch.Ramesh
Embedded Systems 31

32. Tade-offs
The choice of hard ware and soft ware for a perticular function is simply a trade off among various design metrics.
Prof. Ch.Ramesh
Embedded Systems 32

33. Custom Single Purpose Processors: Hardware
A processor a digital circuit designed to perform computation tasks. A processor consists of data path capable of storing and manipulating data and a controller capable of moving data through a data path.
Single purpose processor:
The single purpose processor designed specifically to carry out a perticular computational task.
An embedded system designer may obtain several benefits by choosing to use a custom single purpose processor rather than a general purpose processor to implement a computation task.
Basic techniques in designing a single purpose processors
Prof. Ch.Ramesh
Embedded Systems 33

34. Custom single purpose processor design.
Combinational logic.
Sequential logic.
Custom single purpose processor design.
RT- Level Custom single purpose processor design.
Optimizing Custom single purpose processor design.
Prof. Ch.Ramesh
Embedded Systems 34

35. Combinational Logic Transistors and Logic Gates
Basic combinational Logic Design
RT – Level Combinational Components
Prof. Ch.Ramesh
Embedded Systems 35

36. Transistors and logic gates:
The transistor is the basic electrical component in a digital system. The transistor acts as a simple on/off switch.
Eg : CMOS ( Complementary Metal Oxide semiconductor)
The Gate controls whether or not the current flows from the source to the drain.
Given the basic two transistors we can construct the following digital family gates.
Prof. Ch.Ramesh
Embedded Systems 36

37. x y F=(xy)| e d x y F=(x+y)| a b N MOS Transistor Inverter NAND gate
Source
Drain
Conducts if
gate = 1 x y
F=(xy)| e d x y
F=(x+y)| a
Gate
Source
Drain
Conducts if
gate = o b
N MOS Transistor
Inverter
NAND gate
NOR gate X
F=X c
Prof. Ch.Ramesh
Embedded Systems 37

38. Different types of gates used in digital systems are Driver gate
Inverter
And gate
Nand gate
Or Gate
Nor Gate
Exclusive OR gate
Exclusive NOR gate
Prof. Ch.Ramesh
Embedded Systems 38

39. Basic Combinational Logic Design
A combinational logic circuit is a digital circuit whose output is purely a function of its present inputs. Such a circuit has no memory of past inputs.
We use a simple technique to design a combinational circuit from basic logic gates.
Minimize the output equation to minimize the number of gates used and draw the circuit diagram.
inputs
outputs a b c y z 1
Eg :
Prof. Ch.Ramesh
Embedded Systems 39

40. Y = a|bc + ab|c + abc| + abc Z = a|b|c + a|bc| + abc| + abc1 y z a bc
abc y z
Prof. Ch.Ramesh
Embedded Systems 40

41. RT- Level Combinational Components:
There are several combinational components to reduce the computational complexity. The combinational components include
1. Multiplexer
2. Decoder
3. Adder
4. Comparator
5. Arithmetic Logic Unit
N bit m X 1
Multiplexer s0
Slog(m) n I0
I(m-1) O
Multiplexer:
This is sometimes called as selector. It allows only one of its data inputs to pas through to the output. If there are ‘m’ data inputs then it has log 2m select lines. We call this as m X 1 mux.
Prof. Ch.Ramesh
Embedded Systems 41

42. Decoder:
A decoder converts a binary input into one hot output. If there are n outputs then there must be log2(n) inputs. The decodes is called log2(n) X n decoder. It has an additional input called enable input.
Log(n) X n
Decoder O0 O1 O2
On-1 I0 I1 I2
I(log(n) – 1)
N – bit adder
Carry
Sum A B
Adder:
Adds two n bit numbers A & B generating n bit output sum and a carry. An adder comes with carry as input such adders can be cascaded to produce n bit adder.
Prof. Ch.Ramesh
Embedded Systems 42

43. Arithmetic Logic Unit:B
Comparator:
A comparator compares two n bit binary inputs A and B and generating outputs that indicate whether A is less than grater than or equal . Accordingly the outputs are generated.
n – Bit
Comparator
Less
Equal
Greater
Arithmetic Logic Unit:
It can perform different types of arithmetic and logic functionson the given input bits of A & B.
The select lines are used to select the current function. A B so
N bit
m function
ALU s1
S(log m)
sum
Prof. Ch.Ramesh
Embedded Systems 43

44. Consider the ALU performs the following operations S.No. cin b a s
In the design of ALU define the basic operations of ALU ans define the status of status signal .
Consider the ALU performs the following operations
S.No.
cin b a s
Cout 1 2 3 4 5 6 7
Prof. Ch.Ramesh
Embedded Systems 44

45. s 00 01 11 10 1
cout 00 01 11 10 1
Prof. Ch.Ramesh
Embedded Systems 45

46. Sequential Logic The components of sequential logic are :
1. Flip – Flops
2. RT – Level Sequential Components
3. Sequential Logic Design
Prof. Ch.Ramesh
Embedded Systems 46

47. Flip-Flops :
A sequential circuit is a digital circuit whose outputs are a function of the present as well as previous input values.
One of the most basic sequential circuits are Flip – Flops
A Flip – Flop stores single bit. The simplest type of flip flop is D type Flip Flop.
When the clock is zero the D input is ignored and the out put continue to reflect the stored value.
Another type of Flip – Flop is SR type Flip – Flop
Other Flip – Flop is JK type of Flip Flop where when JK inputs are 1 then the stored bit toggles from 1 to 0 or 0 to 1.
To prevent unexpected behavior from signal glitches the Flip – Flops are designed to be Edge triggered Flip – Flop.
Prof. Ch.Ramesh
Embedded Systems 47

48. RT-Level Seqential Coponents
The components of RT – Level Components are :
Registers
Shift Registers
Counters
n Bit
Register
Load
Clear n Q
Register :
A register stores ‘n’ bit data input and these stored bits appear at its output Q.
A register has at least two control inputs i.e. Clock and load.
For rising edge triggers register the input I are only stored when load is 1 and clock is rising from 0 to 1. the clock is usually drawn as small triangle as shown ion figure.
Because all n bits of the register can be stored in parallel we often refer this type of register is called Parallel Load Register.
Prof. Ch.Ramesh
Embedded Systems 48

49. Shift Register:
It stores n bits but it cannot store them in parallel. The bits must be shifted into the register serially. i.e. one bit per clock.
A shift register has one bit data input and has two control pulses. i.e. clock and shift.
When clock is rising and shift is 1 then the input value is stored in nth position by shifting the nth position bit to n-1 position and so on.
The fist bit that is shifted out will appear at the output Q.
n-bit
shift register
shift I
clock
Q = lsb
Prof. Ch.Ramesh
Embedded Systems 49

50. Counter
Count
Clock
Clear
N bit counter n Q
A counter is a register that can also increment meaning ad 1 to it.
A counter has a clear input which resets the counter to 0.
The count input enables the incrementing on each clock edge.
It has the options to up count and down count.
The control inputs are either synchronous are asynchronous.
Prof. Ch.Ramesh
Embedded Systems 50

51. Sequential logic design:
The points to be noted in sequential logic design are
Problem description
Translate the description into state diagram
Implementation Model
State Table
Minimized output equations
Combinational Logic diagram
Problem description:
Construct a pulse driver. Slow down pre existing pulse so that output a ‘1’ for every four pulses detected.
Prof. Ch.Ramesh
Embedded Systems 51

52. State Diagram (FSM)
Translate the description of the problem into a state diagram. It is called as Finite state machine.
Each state represents the current mode of the circuit serving as the circuits memory of past inputs.
The desired output values are listed next to each state.
The input conditions that causes transition from one state to another is are shown next to each arc.
Each arc condition is implicitly ANDed with the rising edge of the clock. We can say all inputs are synchronous inputs.
All inputs and outputs must be Boolean and all operations are Boolean in nature.
Prof. Ch.Ramesh
Embedded Systems 52

53. Implementation of FSM:
Implement the FSM using Register to store the current state, and combinational logic gate to generate the output values and the next state.
Assign each state a unique binary value and then create a truth table for the combinational logic.
The inputs for the combinational logic are state bits coming from the state register, the external inputs.
The outputs of the combinational logic are the state bits to be loaded into the register on the next clock edge, and the external output values.
State Table:
Prepare the truth table for the inputs and outputs from the implementation model.
Prof. Ch.Ramesh
Embedded Systems 53

54. Minimized output equations:
minimize the truth table sung Karnaugue maps and finally write minimized equations where we can use them for implementation.
Combinational logic:
After minimization implement them using the basic gates.
The following steps are illustrated using the example
Prof. Ch.Ramesh
Embedded Systems 54

55. 3 3 1 2 1 a X Combinational Logic I1 4 State Register I0 2 Q1 Q0 a=0
Inputs
Outputs Q1 Q0 a I1 I0 x 1
State diagram
Implementation model
State table
Combinational Logic
a=0
a=0
x=0
x=1 3
a=1 3
a=1
a=1
a=1 1 2
x=0
x=0
a=0 1
a=0 a X x
Combinational
Logic a I0 I1 Q1 Q0 I1
clk 4
State Register I1 I0 I0 2
Prof. Ch.Ramesh
Embedded Systems 55 Q1 Q0

56. Custom Single Purpose Processor Design:
A basic processor can be built with the above examples. The basic processor consists of
Controller 2. Data path
Controller:
The controller caries out such configuration of data path.
It sets the data path control inputs, like register load and multiplexer select signals, of the register units, functional units, and connection units to obtain the desired configuration at a particular time.
It monitors the external control inputs as well as data path control outputs such as status signals, coming from functional units, and sets external control outputs.
We can apply combinational as well as sequential logic design techniques to build a controller and data path.
Prof. Ch.Ramesh
Embedded Systems 56

57. Single purpose processor consists of a controller and a data path.
The data path stores and manipulates a systems data.
The data in an embedded systems are binary numbers representing external conditions like temperature or speed.
Characters are to be displayed on the screen or digitized photographic images to be stored and compressed.
The data path contains register units like wires and multiplexers.
The data path can be configured to read data from a particular registers, feed that data through functional units configured to carry out particular operation like add or shift and store the operation results back into particular registers.
Note:
Single purpose processor consists of a controller and a data path.
Prof. Ch.Ramesh
Embedded Systems 57

58. A view inside the controller and Data Path
Next-state
And
Control
logic
State
register
registers
Functional
units
controller
Data path
Controller
Data path
External control inputs
External control outputs
External data inputs
External data outputs
data path control inputs
data path control outputs
Controller & Data Path
A view inside the controller and Data Path
Prof. Ch.Ramesh
Embedded Systems 58

59. Design a simple embedded system for finding the GCD
Fig – 1
It is the black box diagram of the desired system having x_i and y_i data imputs and a data output d_o
The output represents the GCD of the inputs.
Fig – 2
It is a simple program with functionality.
The programmer can verify that this program will compute the GCD of the given input.
Fig – 3
To build a single purpose processor
Convert the program into a complex state diagram in which states and arcs may include arithmetic expressions and those expressions may use external inputs and outputs as well as variables.
Prof. Ch.Ramesh
Embedded Systems 59

60. We use templates to convert the program into FSMD.
The more complex state diagram is essentially a sequential program in which statements have been scheduled into states. This complex state diagram is referred as the Finite State Machine With Data.
We use templates to convert the program into FSMD.
After completely defining the FSMD ( Custom Single Purpose Processor) then divide the functionality into
> Data Path part
> Controller part.
Data Path consists of an interconnection of combinational and sequential components.
The controller part consists of Pure FSM that is it contains only boolean actions and conditions.
Prof. Ch.Ramesh
Embedded Systems 60

61. The data path can be constructed through the following steps.
Create a register for any declared variable ( inputs, outputs etc) and draw the input and outputs port.
Create a functional unit for each arithmetic operation in the state diagram.
Connect the ports, Registers and functional units
Create a simple unique identifier for each control input and output of the data path components.
Now that FSM has the same states and transitions as the FSMD.
Replace the complex actions and conditions by Boolean ones, making use of the data path.
Complete the controller design by implementing the FSM using the sequential design technique..
Prof. Ch.Ramesh
Embedded Systems 61

62. !1 State Diagram GCD d_o Desired functionality : Int x,y 1 While (1) {2 2j 3 4 5 6 7 6j 5j 9 1j
y= y-x
x= x-y
d_o=x
!(!go_i)
!go_i
x=x_i
Y=y_i
!(x!=y)
x!=y
x<y
!(x<y) 8 !1
int x,y
State Diagram
go_i
X_i
Y_i
GCD
d_o
Black Box View
Desired functionality :
Int x,y 1
While (1) { 2
while ( !go_i) ; 3
x = x_i; 4
y = y_i; 5
while ( x != y) { 6
if ( x< y ) 7
y = y – x;
else 8
x = x – y; } 9
d_o = x;
Prof. Ch.Ramesh
Embedded Systems 62

63. C: C: J: J: !cond cond a=b Next statement Loop – body statements C1
other
statements J: J:
Next
statement
Next
statement
Prof. Ch.Ramesh
Embedded Systems 63

64. Prof. Ch.Ramesh
Embedded Systems 64

65. 9:d Go_i Clk X_i y_i x_sel=0 X_id=1 y_sel=0 y_id=1 y_sel=1 x_sel=1
D id = 1
x_sel=1 1: 2:
2-j: 3: 4: 5: 6: 8: 7: 9:
6-j:
5-j:
1-j:
!go_i
!(!go_i)
!x neq y
x neq y
!x lt y
x lt y
Controller
To all
registers
Data path
x_sel
N bit 2 x 1
N bit 2 x 1
y_sel
x_id
0 : x
0 : y
y_id !=
<
subtractor
subtractor
x != y
x < y
x-y
y-x
x neq y
x lt y
9:d
d_id
State register
Combinational
Logic
x_sel
y_sel
x_id
y_id
x neq y
x lt y
d_id
Clk Q2 Q1 Q3 Q0 I2 I1 I3 I0
Go_i
d_o
Controller
Implementation
model
Prof. Ch.Ramesh
Embedded Systems 65

66. RT-Level Custom Single Purpose Processor Design
The basic technique of converting a sequential program into a custom single purpose processor is by first converting the program to am FSMD using the provided templates for each language construct splitting the FSMD into simple FSM controlling a data path and performing a sequential logic design on the FSM.
Problem specification:
We want to send the 8bit number to another device.
The problem is that the receiver can receive 8 bits at a time.
The sender sends 4 bits at a time first it sends lower order 4 bits, then the higher order 4 bits.
Need to design a bridge that will enable the two devices to communicate.
The following is the simple problem specification shown in the diagram.
Prof. Ch.Ramesh
Embedded Systems 66

67. Second approach is sequential program
One method of designing consists of Registers, Multiplexers and Flip-flops.
Second approach is sequential program
Most natural method is FSMD approach.
In the design example we considered an FSMD approach.
It consists of waitFirst4 that waits for first 4 bits whose presence on data_in will be indicated by a pulse on rdy_in
Once the pulse is detected , we transition to a state RecFirst4Start that saves the contents of data_in in a variable called dat_lo.
Wait for rdy_in to end. And wait for another 4 bits indicated by a second pulse on rdy_in.
Save the contents of data_in in a vaariable data_hi.
After waiting for the second pulse on rdy_in to end, we then Write the full 8 bits of data to the output data_out and pulse rdy_out.
Every transition in FSMD is anded with clock.
Prof. Ch.Ramesh
Embedded Systems 67

68. Problem Specification
Bridge a single purpose processor
that converts 2 4 bit inputs,
Arriving one at a time over
Data_in along with a rdy_in pulse,
Into one 8 bit output on data_out
Along with a rdy_in pulse
rdy_in
rdy_out
Sender
Receiver
clock
data_in(4)
data_out(8)
FSMD
Bridge
Rdy_in = 0
Rdy_in = 1
WaitFirst4
Rdy_in = 1
RecFirst4start
Data_1o=data_in
recFirst4End
Rdy_in = 0
Rdy_in = 0
Rdy_in = 1
Rdy_in = 1
WaitSeconf4
RecSecond4start
Data_hi=data_in
recSecond4End
Rdy_in = 0
Inputs: Rdy_in:bi; data_in:bit[4]; outputs: rdy_out:bit;data_out:bit[8]; Variable: data_lodata_hi:bit[4]
Send8Start
Data_out=dat_hi
&data_lo
Rdy_out=1
send8End
Rdy_out=0
Prof. Ch.Ramesh
Embedded Systems 68

69. Bridge send8End Rdy_out=0 Data_Path WaitFirst4 recFirst4End
Rdy_in = 0
Rdy_in = 1
WaitFirst4
Rdy_in = 1
RecFirst4start
Data_1o=data_in
recFirst4End
Rdy_in = 0
Rdy_in = 0
Rdy_in = 1
Rdy_in = 1
WaitSeconf4
RecSecond4start
Data_hi=data_in
recSecond4End
Rdy_in = 0
Inputs: Rdy_in:bi; data_in:bit[4]; outputs: rdy_out:bit;data_out:bit[8]; Variable: data_lodata_hi:bit[4]
Send8Start
Data_out=dat_hi
&data_lo
Rdy_out=1
send8End
Rdy_out=0
Rdy_in
Rdy_out
clk
Data_in(4)
Data_out
Data_lo_id
Data_hi_id
Data_hi
Data_lo
Data_out_id
To all registers
Data_out
Data_Path
Prof. Ch.Ramesh
Embedded Systems 69

70. Optimizing Custom Single Purpose Processors
Optimization is the task of making design metric values the best possible. Optimization is the phase in the design of any system. Presently it relates to
Optimizing the original code
Optimizing the FSMD( Finite State Machine with Optimizing the Data)
Optimizing the data path
Optimizing FSM
Prof. Ch.Ramesh
Embedded Systems 70

71. Optimizing the Original Code
We can analyze the number computations required by the algorithm.
Analyze the algorithm in terms of its time complexity
Develop alternative algorithm which is more efficient
The choice of algorithm depends on the efficiency of the designed processor.
int x, y, r;
While(1) {
while ( !go_i);
if ( x_i >= y_i) { x = x_i; y=y_i; }
else
{ x=y_i; y = x_i; }
while ( y != 0 ) { r = x%y; x=y; y=r; }
d_o = x; }
Prof. Ch.Ramesh
Embedded Systems 71

72. Optimizing the FSMD
Once the program was decided then convert the program describing the algorithm in to an FSMD. Many states in the resulting FSMD could likely be merged into fewer states.
Scheduling is the task of assigning operations from the original program to states in an FSMD.
The scheduling is obtained using the template based method can be improved by taking into the consideration of original FSMD
Prof. Ch.Ramesh
Embedded Systems 72

73. Original FSMD and optimizations1 2 2j 3 4 5 6 7 6j 5j 9 1j
y= y-x
x= x-y
d_o=x
!(!go_i)
!go_i
x=x_i
Y=y_i
!(x!=y)
x!=y
x<y
!(x<y) 8
x=x_i
y=y_i
y = y-x
x = x-y
d_o = x
int x,y
go_i
!go_i
x<y
x>y
!(x!=y)
Original FSMD and optimizations
Optimized FSMD
Prof. Ch.Ramesh
Embedded Systems 73

74. Optimizing the data path:
Create unique functional unit for every arithmetic operation in FSMD
Many arithmetic operations in the FSMD can share a single functional unit supports those operations. Those operations occur in different states.
The main task of it is scheduling, allocation of the task and binding the program.
a) Scheduling : it refers to making the program to be available in the ready queue.
b) Allocation : it refers to the which RT components to use in the data path
c) Binding refers to the mapping operations from the FSMD to allocated components
Prof. Ch.Ramesh
Embedded Systems 74

75. Optimizing the FSM
Designing the sequential circuit to implement an FSM also provides opportunities for optimization namely
a) State encoding
b) State minimization
State Encoding : it is the task of assigning a unit bit pattern to each state in FSM. Any assignment in which the encoding are unique will work properly but the size of the state register and the size of the combinational logic may differ for different encodings.
State minimization : it is the task of merging equivalent state into a single state. If two states are equal for all possible input combinations those two states generates the same outputs and transition to the same net state. The state minimization does not change the output behavior in any way.
Prof. Ch.Ramesh
Embedded Systems 75

76. END
Prof. Ch.Ramesh
Embedded Systems 76