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VGA Port CSE 678.

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Presentation on theme: "VGA Port CSE 678."— Presentation transcript:

1 VGA Port CSE 678

2 Raster Scan Displays Electron beam CRT

3 Raster Scan Characters
14 9

4 T 54 H 48 Character E 45 generator Character line 1 Row (40 words or
select 80 bytes) Video Shift register signal Character line 2 (40 words or 80 bytes) even addresses odd addresses

5 Attribute Byte 7 6 5 4 3 2 1 0 BL R G B I R G B Blinking bit
BL R G B I R G B Blinking bit Foreground 0 = not blinking 1 = foreground Intensity bit blinking 0 = normal intensity 1 = high intensity Background

6

7

8 Back porch Back porch Front porch

9 Horizontal Timing 144 784 Pixel clock = 25 MHz Pixel time = 0.04 ms Horizontal video = 640 pixels x 0.04 ms = ms Back porch, BP = 16 pixels x 0.04 ms = 0.64 ms Front porch, FP = 16 pixels x 0.04 ms = 0.64 ms Sync pulse, SP = 128 pixels x 0.04 ms = 5.12.ms Horizontal Scan Lines = SP + BP + HV + FP = = 800 pixels x 0.04 ms = 32 ms 1/60 Hz = ms / 32 ms = 521 horizontal scan lines per frame

10 Vertical Timing 31 511 Pixel clock = 25 MHz Horizontal scan time = 32 ms Vertical video = 480 pixels x 32 ms = ms Back porch, BP = 29 pixels x 32 ms = ms Front porch, FP = 10 pixels x 32 ms = ms Sync pulse, SP = 2 pixels x 32 ms = ms Horizontal Scan Lines = SP + BP + VV + FP = = 521 pixels x 32 ms = ms 1/60 Hz = ms

11 VGA Controller entity vgaController is
Port ( mclk, clr : in std_logic; hs : out std_logic; vs : out std_logic; red : out std_logic; grn : out std_logic; blu : out std_logic); end vgaController;

12 VGA Controller architecture Behavioral of vgaController is
constant hpixels: std_logic_vector(9 downto 0) := " "; --Value of pixels in a horizontal line = 800 constant vlines: std_logic_vector(9 downto 0) := " "; --Number of horizontal lines in the display = 521 constant hbp: std_logic_vector(9 downto 0) := " "; --Horizontal back porch = 144 (128+16) constant hfp: std_logic_vector(9 downto 0) := " "; --Horizontal front porch = 784 ( ) constant vbp: std_logic_vector(9 downto 0) := " "; --Vertical back porch = 31 (2+29) constant vfp: std_logic_vector(9 downto 0) := " "; --Vertical front porch = 511 ( ) signal hc, vc: std_logic_vector(9 downto 0); These are the Horizontal and Vertical counters

13 VGA Controller signal clkdiv : std_logic; --Clock divider
signal vidon : std_logic; Tells whether or not its ok to display data signal vsenable: std_logic; Enable for the Vertical counter begin --This cuts the 50Mhz clock in half process(mclk, clr) if clr = '1' then clkdiv <= '0'; elsif(mclk = '1' and mclk'EVENT) then clkdiv <= not clkdiv; end if; end process;

14 VGA Controller --Runs the horizontal counter process(clkdiv) begin
if clr = '1' then hc <= " "; elsif(clkdiv = '1' and clkdiv'EVENT) then if hc = hpixels then If the counter has reached the end of pixel count hc <= " "; reset the counter vsenable <= '1'; Enable the vertical counter to increment else hc <= hc + 1; Increment the horizontal counter vsenable <= '0'; Leave the vsenable off end if; end process; hs <= '0' when hc(9 downto 7) = "000" else '1'; --Horizontal Sync Pulse is low when hc is

15 VGA Controller --Runs the vertical counter process(clkdiv) begin
if clr = '1' then vc <= " "; elsif(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then --Increment when enabled if vc = vlines then Reset when the number of lines is reached else vc <= vc + 1; --Increment the vertical counter end if; end process; vs <= '0' when vc(9 downto 1) = " " else '1'; --Vertical Sync Pulse is low when vc is 0 or 1

16 VGA Controller red <= '1' when (hc = " " and vidon ='1') else '0'; --Red pixel on at a horizontal count = 684 = grn <= '1' when (hc = " " and vidon ='1') else '0'; --Green pixel on at a horizontal count = 260 = blu <= '1' when (vc = " " and vidon ='1') else '0'; --Blue pixel on at a vertical count = 289 = vidon <= '1' when (((hc < hfp) and (hc > hbp)) and ((vc < vfp) and (vc > vbp))) else '0'; --Enable video out when within the porches end Behavioral;


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