1. Number Representation

2. How to Represent Negative Numbers?
So far, unsigned numbers
Obvious solution: define leftmost bit to be sign!
0 => +, 1 => -
Rest of bits can be numerical value of number
Representation called sign and magnitude

3. Shortcomings of sign and magnitude?
Arithmetic circuit more complicated
Special steps depending whether signs are the same or not
Also, Two zeros
0x = +0ten
0x = -0ten
What would it mean for programming?
Sign and magnitude abandoned

4. Another try: complement the bits
Example: 710 = =
Called one’s Complement
Note: postive numbers have leading 0s, negative numbers have leadings 1s.
00000
00001
01111
...
11111
11110
10000
What is ?
How many positive numbers in N bits?
How many negative ones?

5. Shortcomings of ones complement?
Arithmetic not too hard
Still two zeros
0x = +0ten
0xFFFFFFFF = -0ten
What would it mean for programming?
One’s complement eventually abandoned because another solution was better

6. Search for Negative Number Representation
Obvious solution didn’t work, find another
What is result for unsigned numbers if tried to subtract large number from a small one?
Would try to borrow from string of leading 0s, so result would have a string of leading 1s
With no obvious better alternative, pick representation that made the hardware simple: leading 0s  positive, leading 1s  negative
xxx is >=0, xxx is < 0
This representation called two’s complement

7. Two’s Complement Number line
11111
00000
00001
2 N-1 non-negatives
2 N-1 negatives
one zero
how many positives?
comparison?
overflow?
11110
00010 -1 1 -2 2 . .
-15 15
-16
01111
10001
10000

8. Two’s Complement Numbers
two = 0ten two = 1ten two = 2ten two = 2,147,483,645ten two = 2,147,483,646ten two = 2,147,483,647ten two = –2,147,483,648ten two = –2,147,483,647ten two = –2,147,483,646ten two = –3ten two = –2ten two = –1ten
One zero, 1st bit => >=0 or <0, called sign bit
but one negative with no positive –2,147,483,648ten

9. Two’s Complement Formula
Can represent positive and negative numbers in terms of the bit value times a power of 2:
d31 x d30 x d2 x 22 + d1 x 21 + d0 x 20
Example two
= 1x x230 +1x x22+0x21+0x20 =
= -2,147,483,648ten + 2,147,483,644ten
= -4ten
Note: need to specify width: we use 32 bits

10. Two’s complement shortcut: Negation
Invert every 0 to 1 and every 1 to 0, then add 1 to the result
Sum of number and its one’s complement must be two
two= -1ten
Let x’ mean the inverted representation of x
Then x + x’ = -1  x + x’ + 1 = 0  x’ + 1 = -x
Example: -4 to +4 to -4 x : two x’: two +1: two ()’: two +1: two

11. Two’s comp. shortcut: Sign extension
Convert 2’s complement number using n bits to more than n bits
Simply replicate the most significant bit (sign bit) of smaller to fill new bits
2’s comp. positive number has infinite 0s
2’s comp. negative number has infinite 1s
Bit representation hides leading bits; sign extension restores some of them
16-bit -4ten to 32-bit:
two
two

12. Addition of Positive Numbers

13. Carries a: 0 0 1 1 b: 0 1 0 1 Sum: 1 0 0 0 One-Bit Full Adder (1/3)
Example Binary Addition:
Carries a: b:
Sum:
Thus for any bit of addition:
The inputs are ai, bi, CarryIni
The outputs are Sumi, CarryOuti
Note: CarryIni+1 = CarryOuti

14. Definition One-Bit Full Adder (2/3)
Sum = ABCin + ABCin + ABCin + ABCin
CarryOut = AB + ACin + BCin
¯ ¯ ¯ ¯ ¯ ¯

15. CarryIn A + Sum B CarryOut One-Bit Full Adder (3/3)
To create one-bit full adder:
implement gates for Sum
implement gates for CarryOut
connect all inputs with same name
Sum A B
CarryIn
CarryOut +

16. Ripple-Carry Adders: adding n-bits numbers
CarryIn0 A0
1-bit FA
Sum0 B0
CarryOut0
CarryIn1 A1
1-bit FA
Sum1 B1
CarryOut1
CarryIn2 A2
1-bit FA
Sum2 B2
CarryOut2
CarryIn3 A3
1-bit FA
Sum3 B3
CarryOut3
Critical Path of n-bit Rippled-carry adder is n*CP
CP = 2 gate-delays (Cout = AB + ACin + BCin)

17. Fast Adders

18. Carry Look Ahead: reducing Carry Propagation delay
A B C-out
0 0 0 “kill”
0 1 C-in “propagate”
1 0 C-in “propagate”
1 1 1 “generate” A0 B0 S0 G P
P = A + B
G = A  B
Cin A B S G P
C1 = G0 + C0 · P0
= A0B0 + C0(A0+B0)
C2 = G1 + G0 · P1 + C0 · P0 · P1
C3 = G2 + G1 · P2 + G0 · P1 · P2 + C0 · P0 · P1 · P2
G = G3 + P3·G2 + P3·P2·G1 + P3·P2·P1·G0
C4 = . . .
P = P3·P2·P1·P0
Names: suppose G0 is 1 => carry no matter what else => generates a carry
suppose G0 =0 and P0=1 => carry IFF C0 is a 1 => propagates a carry
Like dominoes
What about more than 4 bits?

19. Carry Look Ahead: Delays
Expression for any carry:
Ci+1 = Gi + PiGi-1 + … + PiPi-1 … P0C0
All carries can be obtained in 3 gate-delays:
1 needed to developed all Pi and Gi
2 needed in the AND-OR circuit
All sums can be obtained in 6 gate-delays:
3 needed to obtain carries
1 needed to invert carry
2 needed in the AND-OR circuit of Sum’s circuit
Independent of the number of bits (n)
4-bit Adder:
CLA: 6 gate-delays
RC: (3*2 + 3) gate-delays
Sum = ABCin + ABCin + ABCin + ABCin
¯ ¯ ¯ ¯ ¯ ¯
16-bit Adder:
CLA: 6 gate-delays
RC: (15*2 + 3) gate-delays

20. Cascaded CLA: overcoming Fan-in constraintP0
C1 = G0 + C0 · P0
4-bit
Adder
Delay = = 8
DelayRC = 15*2 + 3 = 33
C2 = G1 + G0 · P1 + C0 · P0 · P1
4-bit
Adder
C3 = G2 + G1 · P2 + G0 · P1 · P2 + C0 · P0 · P1 · P2
4-bit
Adder G P
C4 = . . .

21. Signed Addition & Subtraction

22. Addition & Subtraction Operations
Just add the two numbers
Ignore the Carry-out from MSB
Result will be correct, provided there’s no overflow
Subtraction:
Form 2’s complement of the subtrahend
Add the two numbers as in Addition
(+5) (+2) (+7)
(+5) (-6) (-1)
(+2)  (+4) (-4) (-2)
(-5) (-2) (-7)
(+7) (-3) (+4)
(-2)  (-5) (+5) (+3)

23. Overflow Examples: 7 + 3 = 10 but ... - 4  5 = - 9 but ... Decimal
Binary
Decimal
2’s Complement
0000
0000 1
0001 -1
1111 2
0010 -2
1110 3
0011 -3
1101 4
0100 -4
1100 5
0101 -5
1011 6
0110 -6
1010 7
0111 -7
1001 -8
1000
Examples: = but ...
- 4  5 = but ...
Well so far so good but life is not always perfect.
Let’s consider the case 7 plus 3, you will get 10.
But if you perform the binary arithmetics on our 4-bit adder you will get 1010, which is negative 6.
Similarly, if you try to add negative 4 and negative 5 together, you should get negative 9.
But the binary arithmetics will give you 0111, which is 7.
So what went wrong? The problem is overflow.
The number you get are simply too big, in the positive 10 case, and too small in the negative 9 case, to be represented by four bits.
+2 = 39 min. (Y:19) 1 1 1 1 1 1 1 7 1 1
– 4 3
– 5 + 1 1 + 1 1 1 1 1
– 6 1 1 1 7

24. Overflow Detection
Overflow: the result is too large (or too small) to represent properly
Example: - 8 < = 4-bit binary number <= 7
When adding operands with different signs, overflow cannot occur!
Overflow occurs when adding:
2 positive numbers and the sum is negative
2 negative numbers and the sum is positive
On your own: Prove you can detect overflow by:
Carry into MSB ° Carry out of MSB
Recalled from some earlier slides that the biggest positive number you can represent using 4-bit is 7 and the smallest negative you can represent is negative 8.
So any time your addition results in a number bigger than 7 or less than negative 8, you have an overflow.
Keep in mind is that whenever you try to add two numbers together that have different signs, that is adding a negative number to a positive number, overflow can NOT occur.
Overflow occurs when you to add two positive numbers together and the sum has a negative sign. Or, when you try to add negative numbers together and the sum has a positive sign.
If you spend some time, you can convince yourself that If the Carry into the most significant bit is NOT the same as the Carry coming out of the MSB, you have a overflow.
+2 = 41 min. (Y:21) 1 1 1 1 1 1 1 7 1 1 –4 3
– 5 + 1 1 + 1 1 1 1 1
– 6 1 1 1 7

25. Overflow Detection Logic
Carry into MSB ° Carry out of MSB
For a N-bit Adder: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
CarryIn0 A0
1-bit FA
Result0 X Y
X XOR Y B0 A1 B1
1-bit FA
Result1
CarryIn1
CarryOut1
CarryOut0 1 1 1 1 1 1
CarryIn2
Recall the XOR gate implements the not equal function: that is, its output is 1 only if the inputs have different values.
Therefore all we need to do is connect the carry into the most significant bit and the carry out of the most significant bit to the XOR gate.
Then the output of the XOR gate will give us the Overflow signal.
+1 = 42 min. (Y:22) A2
1-bit FA
Result2 B2
CarryIn3
Overflow A3
1-bit FA
Result3 B3
CarryOut3

26. Arithmetic & Branching Conditions

27. CC Flags will be set/cleared by arithmetic operations:
Condition Codes
CC Flags will be set/cleared by arithmetic operations:
N (negative): 1 if result is negative (MSB = 1), otherwise 0
C (carry): 1 if carry-out(borrow) is generated, otherwise 0
V (overflow): 1 if overflow occurs, otherwise 0
Z (zero): 1 if result is zero, otherwise 0
(+5) (-6) (-1)
(+5) (+4) (-7?)
(+7) (-3) (+4)
(+3) (-3) (0)

28. Multiplication of Positive Numbers

29. Unsigned Multiplication
Paper and pencil example (unsigned):
Multiplicand (13) Multiplier (11) Product (143)
m bits x n bits = m+n bit product
Binary makes it easy:
0 => place ( 0 x multiplicand)
1 => place a copy ( 1 x multiplicand)

30. Unsigned Combinational Multiplier
Stage i accumulates A * 2 i if Bi == 1

31. How does it work? at each stage shift A left ( x 2)A0 A1 A2 A3 B0 A0 A1 A2 A3 B1 A0 A1 A2 A3 B2 A0 A1 A2 A3 B3 P7 P6 P5 P4 P3 P2 P1 P0
at each stage shift A left ( x 2)
use next bit of B to determine whether to add in shifted multiplicand
accumulate 2n bit partial product at each stage

32. Multiplier Circuit 4 bits Multiplicand Shift Right Control 4-bit FA
MUX
Shift Right
Control
4-bit FA
Add/NoAdd C
Product
(Multiplier)
8 bits
Multiplicand
C Product Multiplier Add Shift
Add Shift
NoAdd Shift
Add Shift
4 bits

33. Signed-Operand & Multiplication

34. Signed Multiplication
Negative Multiplicand:
Multiplicand (-13) Multiplier (+11) Product (-143)
Negative Multiplier:
Form 2’s complement of both multiplier and multiplicand
Proceed as above

35. Motivation for Booth’s Algorithm
Works well for both Negative & Positive Multipliers
Example 2 x 6 = 0010 x 0110: x shift (0 in multiplier) add (1 in multiplier) add (1 in multiplier) shift (0 in multiplier)
FA with add or subtract gets same result in more than one way: 6 = – = – =
For example
x shift (0 in multiplier) sub (first 1 in multpl.) shift (mid string of 1s) add (prior step had last 1)

36. Booth’s Algorithm Current Bit Bit to the Right Explanation Example Op
Begins run of 1s sub
Middle of run of 1s none
End of run of 1s add
Middle of run of 0s none
Originally for Speed (when shift was faster than add)
Small number of additions needed when multiplier has a few large blocks of 1s

37. Booths Example (2 x 7) Operation Multiplicand Product next?
0. initial value > sub
1a. P = P - m shift P (sign ext)
1b > nop, shift
> nop, shift
> add 4a
shift
4b done

38. Booths Example (2 x -3) Operation Multiplicand Product next?
0. initial value > sub
1a. P = P - m shift P (sign ext)
1b > add
2a shift P
2b > sub
3a shift
3b > nop
4a shift
4b done

39. Fast Multiplication (read yourself!)

40. Integer Division

41. Divide: Paper & Pencil 1001 Quotient
Divisor Dividend – – Remainder (or Modulo result)
See how big a number can be subtracted, creating quotient bit on each step
Binary => 1 * divisor or 0 * divisor
Dividend = Quotient x Divisor + Remainder => | Dividend | = | Quotient | + | Divisor |

42. Division Circuit Divisor 33 bits Shift Left Control 33-bit FA
Q Setting
Remainder
(Quotient)
65 bits
33 bits
Sign-bit Checking

43. Restoring Division Algorithm
Remainder Quotient
Initially Shift _ Sub(-11) Set q Restore
Shift _ Sub(-11) Set q Restore
Shift _ Sub(-11) Set q
Shift _ Sub(-11) _ Set q Restore
0010 Quotient Divisor Dividend Remainder