1. Morgan Kaufmann Publishers Parallel Processors from Client to Cloud
1 July, 2019
Chapter 6
Parallel Processors from Client to Cloud
Chapter 7 — Multicores, Multiprocessors, and Clusters

2. Morgan Kaufmann Publishers
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Introduction
§6.1 Introduction
Goal: connecting multiple computers to get higher performance
Multiprocessors
Scalability, availability, power efficiency
Task-level (process-level) parallelism
High throughput for independent jobs
Parallel processing program
Single program run on multiple processors
Multicore microprocessors
Chips with multiple processors (cores)
Chapter 6 — Parallel Processors from Client to Cloud — 2
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Hardware and Software
Hardware
Serial: e.g., Pentium 4
Parallel: e.g., quad-core Xeon e5345
Software
Sequential: e.g., matrix multiplication (but, can be multithreaded)
Concurrent: e.g., operating system
Sequential/concurrent software can run on serial/parallel hardware
Challenge: making effective use of parallel hardware
Chapter 6 — Parallel Processors from Client to Cloud — 3
Chapter 7 — Multicores, Multiprocessors, and Clusters

4. What We’ve Already Covered
Morgan Kaufmann Publishers
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What We’ve Already Covered
§2.11: Parallelism and Instructions
Synchronization (e,g. read-modify-write inst.)
§3.6: Parallelism and Computer Arithmetic
Subword Parallelism (e.g. Intel MMX, SSE)
§4.10: Parallelism and Advanced Instruction-Level Parallelism
§5.10: Parallelism and Memory Hierarchies (multicore)
Cache Coherence
Chapter 6 — Parallel Processors from Client to Cloud — 4
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Parallel Programming
Parallel software is the problem
Need to get significant performance improvement
Otherwise, just use a faster uniprocessor, since it’s easier!
Difficulties
Partitioning
Coordination
Communications overhead
§6.2 The Difficulty of Creating Parallel Processing Programs
Chapter 6 — Parallel Processors from Client to Cloud — 5
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Amdahl’s Law
Sequential part can limit speedup
Example: 100 processors, 90× speedup?
Tnew = Tparallelizable/100 + Tsequential
Solving: Fparallelizable = 0.999
Need sequential part to be 0.1% of original time
Chapter 6 — Parallel Processors from Client to Cloud — 6
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Scaling Example
Workload: sum of 10 scalars, and 10 × 10 matrix sum
Speed up from 10 to 100 processors
Single processor: Time = ( ) × tadd
10 processors
Time = 10 × tadd + 100/10 × tadd = 20 × tadd
Speedup = 110/20 = 5.5 (55% of potential)
100 processors
Time = 10 × tadd + 100/100 × tadd = 11 × tadd
Speedup = 110/11 = 10 (10% of potential)
Assumes load can be balanced across processors
Chapter 6 — Parallel Processors from Client to Cloud — 7
Chapter 7 — Multicores, Multiprocessors, and Clusters

8. Scaling Example (cont.)
Morgan Kaufmann Publishers
1 July, 2019
Scaling Example (cont.)
What if matrix size is 100 × 100?
Single processor: Time = ( ) × tadd
10 processors
Time = 10 × tadd /10 × tadd = 1010 × tadd
Speedup = 10010/1010 = 9.9 (99% of potential)
100 processors
Time = 10 × tadd /100 × tadd = 110 × tadd
Speedup = 10010/110 = 91 (91% of potential)
Assuming load balanced
Chapter 6 — Parallel Processors from Client to Cloud — 8
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Strong vs Weak Scaling
Strong scaling: problem size fixed
As in previous example
Weak scaling: problem size proportional to number of processors
10 processors, 10 × 10 matrix
Time = 20 × tadd
100 processors, 32 × 32 matrix
Time = 10 × tadd /100 × tadd = 20 × tadd
Constant performance in this example
Chapter 6 — Parallel Processors from Client to Cloud — 9
Chapter 7 — Multicores, Multiprocessors, and Clusters

10. Instruction and Data Streams
Morgan Kaufmann Publishers
1 July, 2019
Instruction and Data Streams
An alternate classification: parallel system
Data Streams
Single
Multiple
Instruction Streams
SISD: Intel Pentium 4
SIMD: SSE instructions of x86
MISD: No examples today
MIMD: Intel Xeon e5345
§6.3 SISD, MIMD, SIMD, SPMD, and Vector
SPMD: Single Program Multiple Data
A parallel program on a MIMD computer
Conditional code for different processors
Chapter 6 — Parallel Processors from Client to Cloud — 10
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Vector Processors
Highly pipelined function units
Stream data from/to vector registers (with multiple elements in a vector register) to units
Data collected from memory into registers
Results stored from registers to memory
Example: Vector extension to MIPS
32 × 64-element registers (64-bit elements)
Vector instructions
lv, sv: load/store to /from vector registers
addv.d: add vectors of double
addvs.d: add scalar to each element of vector of double
Significantly reduces instruction-fetch bandwidth
Chapter 6 — Parallel Processors from Client to Cloud — 11
Chapter 7 — Multicores, Multiprocessors, and Clusters

12. Example: DAXPY (Y = a × X + Y)
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Example: DAXPY (Y = a × X + Y)
Conventional MIPS code
l.d $f0,a($sp) ;load scalar a addiu r4,$s0,# ;upper bound of what to load loop: l.d $f2,0($s0) ;load x(i) mul.d $f2,$f2,$f0 ;a × x(i) l.d $f4,0($s1) ;load y(i) add.d $f4,$f4,$f2 ;a × x(i) + y(i) s.d $f4,0($s1) ;store into y(i) addiu $s0,$s0,#8 ;increment index to x addiu $s1,$s1,#8 ;increment index to y subu $t0,r4,$s0 ;compute bound bne $t0,$zero,loop ;check if done
Vector MIPS code (Produce 64 results)
l.d $f0,a($sp) ;load scalar a lv $v1,0($s0) ;load vector x (load 64 data) mulvs.d $v2,$v1,$f0 ;vector-scalar multiply lv $v3,0($s1) ;load vector y addv.d $v4,$v2,$v3 ;add y to product sv $v4,0($s1) ;store the result
Chapter 6 — Parallel Processors from Client to Cloud — 12
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Vector vs. Scalar
Vector architectures and compilers
Simplify data-parallel programming
Explicit statement of absence of loop-carried dependences
Reduced checking in hardware
Regular access patterns benefit from interleaved and burst memory
Avoid control hazards by avoiding loops
More general than ad-hoc media extensions (such as MMX, SSE)
Better match with compiler technology
Chapter 6 — Parallel Processors from Client to Cloud — 13
Chapter 7 — Multicores, Multiprocessors, and Clusters

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SIMD
Operate elementwise on vectors of data
E.g., MMX and SSE instructions in x86
Multiple data elements in 128-bit wide registers
All processors execute the same instruction at the same time
Each with different data address, etc.
Simplifies synchronization
Reduced instruction control hardware
Works best for highly data-parallel applications, such as media applications
Chapter 6 — Parallel Processors from Client to Cloud — 14
Chapter 7 — Multicores, Multiprocessors, and Clusters

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SIMD Extensions
Media applications operate on data types narrower than the native word size
Example: disconnect carry chains to “partition” adder
Limitations, compared to vector instructions:
Number of data operands encoded into op code
No sophisticated addressing modes (strided, scatter-gather)
Limited parallelism (register width, e.g. 128 bits)
No mask registers (No if type)
SIMD Instruction Set Extensions for Multimedia
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

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SIMD Implementations
Implementations:
Intel MMX (1996)
Eight 8-bit integer ops or four 16-bit integer ops
Streaming SIMD Extensions (SSE) (1999)
Eight 16-bit integer ops
Four 32-bit integer/fp ops or two 64-bit integer/fp ops
Advanced Vector Extensions (2010) (Fig. 3.20)
Four 64-bit integer/fp ops
Operands must be consecutive and aligned memory locations
SIMD Instruction Set Extensions for Multimedia
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

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Example SIMD Code
Example DAXPY: (4D means 4 double-p. operands)
L.D F0,a ;load scalar a
MOV F1, F0 ;copy a into F1 for SIMD MUL
MOV F2, F0 ;copy a into F2 for SIMD MUL
MOV F3, F0 ;copy a into F3 for SIMD MUL
DADDIU R4,Rx,#512 ;last address to load
Loop: L.4D F4,0[Rx] ;load X[i], X[i+1], X[i+2], X[i+3]
MUL.4D F4,F4,F0 ;a×X[i],a×X[i+1],a×X[i+2],a×X[i+3]
; F4*F0, F5*F1, F6*F2, F7*F3
L.4D F8,0[Ry] ;load Y[i], Y[i+1], Y[i+2], Y[i+3]
ADD.4D F8,F8,F4 ;a×X[i]+Y[i], ..., a×X[i+3]+Y[i+3]
S.4D 0[Ry],F8 ;store into Y[i], Y[i+1], Y[i+2], Y[i+3]
DADDIU Rx,Rx,#32 ;increment index to X
DADDIU Ry,Ry,#32 ;increment index to Y
DSUBU R20,R4,Rx ;compute bound
BNEZ R20,Loop ;check if done
SIMD Instruction Set Extensions for Multimedia
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

18. Vector vs. Multimedia Extensions
Vector instructions have a variable vector width, multimedia extensions (SIMD) have a fixed width
Vector instructions support strided access, multimedia extensions do not
Vector units can be combination of pipelined and arrayed functional units:
Exploit parallelism in a single vector
Chapter 6 — Parallel Processors from Client to Cloud — 18

19. Parallel Lanes for Vector Unit
Vector unit can be structure with multiple lanes to father improve execution time with parallelism
Chapter 6 — Parallel Processors from Client to Cloud — 19

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Multithreading
Performing multiple threads of execution in parallel
Replicate registers, PC, etc.
Fast switching between threads
Fine-grain multithreading
Switch threads after each cycle
Interleave instruction execution
If one thread stalls, others are executed
Coarse-grain multithreading
Only switch on long stall (e.g., L2-cache miss)
Simplifies hardware, but doesn’t hide short stalls (eg, data hazards)
§6.4 Hardware Multithreading
Chapter 6 — Parallel Processors from Client to Cloud — 20
Chapter 7 — Multicores, Multiprocessors, and Clusters

21. Simultaneous Multithreading
Morgan Kaufmann Publishers
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Simultaneous Multithreading
In multiple-issue dynamically scheduled processor
Schedule instructions from multiple threads
Instructions from independent threads execute when function units are available
Within threads, dependencies handled by scheduling and register renaming
Example: Intel Pentium-4 HT (Hyper-threading)
Two threads: duplicated registers, shared function units and caches
Chapter 6 — Parallel Processors from Client to Cloud — 21
Chapter 7 — Multicores, Multiprocessors, and Clusters

22. Multithreading Example
Morgan Kaufmann Publishers
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Multithreading Example
Chapter 6 — Parallel Processors from Client to Cloud — 22
Chapter 7 — Multicores, Multiprocessors, and Clusters

23. Multi-issued / Multithreaded Categories
Simultaneous
Multithreading
Superscalar
Fine-Grained
Coarse-Grained
Multiprocessing
Time (processor cycle)
Single thread
4 Issue slots
Thread 1
Thread 3
Thread 5
Thread 2
Thread 4
Idle slot

24. Simultaneous Multithreading (SMT)
Simultaneous multithreading (SMT): insight that dynamically scheduled processor already has many HW mechanisms to support multithreading
Large set of virtual registers that can be used to hold the register sets of independent threads
Register renaming provides unique register identifiers, so instructions from multiple threads can be mixed in datapath
Out-of-order completion allows the threads to execute out of order, and get better utilization of the HW
Just adding a per thread renaming table and keeping separate PCs
Independent commitment can be supported by logically keeping a separate reorder buffer for each thread
Fetch / Issue from multiple thread pre cycle

25. Copyright © 2014 Elsevier Inc. All rights reserved.
FIGURE 6.6 The speed-up from using multithreading on one core on an i7 processor averages 1.31 for the PARSEC benchmarks (see Section 6.9) and the energy efficiency improvement is This data was collected and analyzed by Esmaeilzadeh et. al. [2011]. 25
Copyright © 2014 Elsevier Inc. All rights reserved.

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Handling Memory Wall
Processors
Exploit MLP (memory level parallelism)
Caches
intelligent cache management, non-blocking
Prefetching
Prefetch instruction and data before use
Accuracy, timely, polution&bandwidth
Multithreading
Hide memory latency with multiple threads
Chapter 6 — Parallel Processors from Client to Cloud — 26
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Shared Memory
SMP: shared memory multiprocessor (multicore)
Hardware provides single physical address space for all processors
Synchronize shared variables using locks
Memory access time
UMA (uniform) vs. NUMA (nonuniform)
§6.5 Multicore and Other Shared Memory Multiprocessors
Chapter 6 — Parallel Processors from Client to Cloud — 27
Chapter 7 — Multicores, Multiprocessors, and Clusters

28. Morgan Kaufmann Publishers
Parallel Programming Example: Sum Reduction on Share-memory Parallel Systems
1 July, 2019
Sum 100,000 numbers on 100 processor UMA
Each processor has ID: 0 ≤ Pn ≤ 99
Partition 1000 numbers per processor
Initial summation on each processor
sum[Pn] = 0; for (i = 1000*Pn; i < 1000*(Pn+1); i = i + 1) sum[Pn] = sum[Pn] + A[i];
Now need to add these partial sums
Reduction: divide and conquer
Half the processors add pairs, then quarter, …
Need to synchronize between reduction steps
Chapter 6 — Parallel Processors from Client to Cloud — 28
Chapter 7 — Multicores, Multiprocessors, and Clusters

29. Example: Sum Reduction
Morgan Kaufmann Publishers
1 July, 2019
Example: Sum Reduction
half = 100;
Repeat /* parallel */
synch();
if (half%2 != 0 && Pn == 0)
sum[0] = sum[0] + sum[half-1];
/* Conditional sum needed when half is odd;
Processor0 gets missing element */
half = half/2; /* dividing line on who sums */
if (Pn < half) sum[Pn] = sum[Pn] + sum[Pn+half];
until (half == 1);
Chapter 6 — Parallel Processors from Client to Cloud — 29
Chapter 7 — Multicores, Multiprocessors, and Clusters

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GPU Architectures
Processing is highly data-parallel
GPUs are highly multithreaded
Use thread switching to hide memory latency
Less reliance on multi-level caches
Graphics memory is wide and high-bandwidth
Trend toward general purpose GPUs
Heterogeneous CPU/GPU systems
CPU for sequential code, GPU for parallel code
Programming languages/APIs
DirectX, OpenGL
C for Graphics (Cg), High Level Shader Language (HLSL)
Compute Unified Device Architecture (CUDA)
Open CL
Chapter 6 — Parallel Processors from Client to Cloud — 30
Chapter 7 — Multicores, Multiprocessors, and Clusters

31. Comparison: GPU vs Multicore CPU
Difference in utilizing on-chip transistors:
CPU has significant cache space and control logic for general- purpose applications
GPU builds large number of replicated cores for data-parallel, thread-parallel computations; requires higher DRAM bandwidth

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History of GPUs
Early video cards
Frame buffer memory with address generation for video output
3D graphics processing
Originally high-end computers (e.g., SGI)
Moore’s Law  lower cost, higher density
3D graphics cards for PCs and game consoles
Graphics Processing Units
Processors oriented to 3D graphics tasks
Vertex/pixel processing, shading, texture mapping, rasterization
§6.6 Introduction to Graphics Processing Units
Chapter 6 — Parallel Processors from Client to Cloud — 32
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Graphics in the System
Chapter 6 — Parallel Processors from Client to Cloud — 33
Chapter 7 — Multicores, Multiprocessors, and Clusters

34. An Example of Physical Reality Behind CUDA – Host Motherboard
CPU
(host)
GPU w/
local DRAM
(device)
GPU

35. G80 – Graphics Mode The future of GPUs is programmable processing
So – build the architecture around the processor L2 FB SP L1 TF
Thread Processor
Vtx Thread Issue
Setup / Rstr / ZCull
Geom Thread Issue
Pixel Thread Issue
Input Assembler
Host

36. G80 CUDA mode – A Device Example
GPGPU - Processors execute general computing threads programmed using CUDA
New operating mode/HW interface for computing
Load/store
Global Memory
Thread Execution Manager
Input Assembler
Host
Texture
Parallel Data Cache
Shared the same hardware with
graphics applications

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Nvidia GPU Family
GeForce: GTX serious for Graphics applications
Tesla: for GPGPU, data center applications
Quadro (Tegra): for mobile devices
Architecture generation:
G80
GT200
Feimi
Kepler
Graphical Processing Units
Copyright © 2012, Elsevier Inc. All rights reserved.
Chapter 2 — Instructions: Language of the Computer

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Example: NVIDIA Tesla
Streaming multiprocessor
8 × Streaming processors
Note, Fermi generation get rid of TPC level
Chapter 6 — Parallel Processors from Client to Cloud — 38
Chapter 7 — Multicores, Multiprocessors, and Clusters

39. Streaming Multiprocessor in Fermi
Two Warp schedulers and Dispatch units
16KB register files
Shared instruction cache
64 KB Shared L1 data cache and Shared (local) memory
Two sets of ALU, 16 cores each (2 cycle initiation latency)
One set of LD/ST, 16 units each (2 cycle latency)
Four SFUs (8 cycle latency)
Separate INT, FP units in each core 39

40. Copyright © 2014 Elsevier Inc. All rights reserved.
Streaming Multiprocessors
FIGURE 6.9 Simplified block diagram of the datapath of a multithreaded SIMD Processor. It has 16 SIMD lanes. The SIMD Thread Scheduler has many independent SIMD threads that it chooses from to run on this processor. 40
Copyright © 2014 Elsevier Inc. All rights reserved.

41. CUDA Programming Model
Host invokes Kernels/Grids to execute on GPU, back to Host after execution
Three-level parallelism: Grid (Kernal), Block, Thread
Thread
Application
Host execution
kernel 0
Block 0
Block 1
Block 2
Block 3
...
...
...
...
After introducing state-of-art CMPs and GPUs, I like to move on to the GPU programming and its performance issues. CUDA is a C-like programming language used on Nvidia GPUs. CUDA has a set of extensions for parallelization , data communication and synchronization. Programs start from the host CPU. Host can invoke a kernel call (also called a grid) to initiate program to run on GPU. After completion, the kernel returns back to the host. Multiple kernels can be initiated by the host to provide parallelism. . There are three levels of parallelization in CUDA: grid, block and thread. The kernal is also referred as a grid. The programmer can further parallelize the kernel into blocks and each block can have multiple threads. As illustrated, an application starts from the host, then invoke a kernel execution, after completion, it returns back to the host. After some computation, it can invoke another kernel, etc. Within a kernel which also referred as a grid, there are two level of parallelism, blocks and threads within a block. These two dimensions of parallelization gives the programmers the flexibility on how they want to parallelize their program.
Host execution
kernel 1
Block 0
Block N … …
...
... …

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Threads and Blocks
A thread is associated with each data element
Threads are organized into blocks, which are scheduled to run on MS (Streaming Multiprocessor)
warps in hardware as a scheduling unit, each block has multiple warps to be scheduled on CP groups to provide multithreading capacity to hide latency.
Each warp has 32 threads to be executed in parallel called SIMT (Single Inst Multiple Thread) on a CP group, similar to vector instruction.
Blocks are organized into a grid (Kernel) to be executed on GPU.
GPU hardware handles thread scheduling and management, not applications or OS.
Graphical Processing Units
Chapter 2 — Instructions: Language of the Computer

43. CUDA Programming Model
Host invokes Kernels/Grids to execute on GPU, back to Host after execution
Three-level parallelism: Grid (Kernal), Block, Thread
Important: GPU programming relies on programs to optimize the execution including three-level parallelization, data moves, register and memory usage, handling control divergence, etc.
While CPU hides most of the complexity from programmers
After introducing state-of-art CMPs and GPUs, I like to move on to the GPU programming and its performance issues. CUDA is a C-like programming language used on Nvidia GPUs. CUDA has a set of extensions for parallelization , data communication and synchronization. Programs start from the host CPU. Host can invoke a kernel call (also called a grid) to initiate program to run on GPU. After completion, the kernel returns back to the host. Multiple kernels can be initiated by the host to provide parallelism. . There are three levels of parallelization in CUDA: grid, block and thread. The kernal is also referred as a grid. The programmer can further parallelize the kernel into blocks and each block can have multiple threads. As illustrated, an application starts from the host, then invoke a kernel execution, after completion, it returns back to the host. After some computation, it can invoke another kernel, etc. Within a kernel which also referred as a grid, there are two level of parallelism, blocks and threads within a block. These two dimensions of parallelization gives the programmers the flexibility on how they want to parallelize their program.

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Example: NVIDIA Tesla
Streaming Processors
Single-precision FP and integer units
Each SP is fine-grained multithreaded
Warp: group of 32 threads
Executed in parallel, SIMD style
8 SPs × 4 clock cycles
Hardware contexts for 24 warps
Registers, PCs, …
Chapter 6 — Parallel Processors from Client to Cloud — 44
Chapter 7 — Multicores, Multiprocessors, and Clusters

45. Comparison: G80, GT200, Fermi
Three classes of hardware: GeForce®, Quadro®, and Tesla® 45

46. Comparison: Kepler vs Fermi
GTX 680
GTX 580
GTX 560 Ti
GTX 480
Stream Processors
1536
512
384
480
Texture Units
128 64 60
ROPs 32 48
Core Clock
1006MHz
772MHz
822MHz
700MHz
Shader Clock
N/A
1544MHz
1644MHz
1401MHz
Boost Clock
1058MHz
Memory Clock
6.008GHz
GDDR5
4.008GHz
4.008GHz GDDR5
3.696GHz GDDR5
Memory Bus Width
256-bit
384-bit
Frame Buffer
2GB
1.5GB
1GB
FP64
1/24 FP32
1/8 FP32
1/12 FP32
TDP
195W
244W
170W
250W
Transistor Count
3.5B 3B
1.95B
Manufacturing Process
TSMC 28nm
TSMC 40nm
Launch Price
$499
$249 46

47. Comparison: Fermi, Kepler47

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Classifying GPUs
Don’t fit nicely into SIMD/MIMD model
Conditional execution in a thread allows an illusion of MIMD
But with performance degredation
Need to write general purpose code with care
Static: Discovered at Compile Time
Dynamic: Discovered at Runtime
Instruction-Level Parallelism
VLIW
Superscalar
Data-Level Parallelism
SIMD or Vector
Tesla Multiprocessor
Chapter 6 — Parallel Processors from Client to Cloud — 48
Chapter 7 — Multicores, Multiprocessors, and Clusters

49. GPU Memory Structures Per-SM with L1 cache
Chapter 6 — Parallel Processors from Client to Cloud — 49

50. CUDA Memory Model Overview
Global memory (also called device memory)
Main means of communicating R/W Data between host and device
Contents visible to all threads
Long latency access
We will focus on global memory for now
Constant and texture memory will come later
Grid
Block (0, 0)‏
Block (1, 0)‏
Shared Memory
Shared Memory
Registers
Registers
Registers
Registers
Thread (0, 0)‏
Thread (1, 0)‏
Thread (0, 0)‏
Thread (1, 0)‏
Host
Global Memory

51. Putting GPUs into Perspective
Feature
Multicore with SIMD
GPU
SIMD processors
4 to 8
8 to 16
SIMD lanes/processor
2 to 4
Multithreading hardware support for SIMD threads
16 to 32
Typical ratio of single precision to double-precision performance
2:1
Largest cache size
8 MB
0.75 MB
Size of memory address
64-bit
Size of main memory
8 GB to 256 GB
4 GB to 6 GB
Memory protection at level of page
Yes
Demand paging No
Integrated scalar processor/SIMD processor
Cache coherent
Chapter 6 — Parallel Processors from Client to Cloud — 51

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i7-960 vs. NVIDIA Tesla 280/480
TSMC
§6.11 Real Stuff: Benchmarking and Rooflines i7 vs. Tesla
Chapter 6 — Parallel Processors from Client to Cloud — 52
Chapter 7 — Multicores, Multiprocessors, and Clusters

53. Message Passing – Different Parallel Computing Model
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Each processor has private physical address space
Hardware sends/receives messages between processors
§6.7 Clusters, WSC, and Other Message-Passing MPs
Chapter 6 — Parallel Processors from Client to Cloud — 53
Chapter 7 — Multicores, Multiprocessors, and Clusters

54. Loosely Coupled Clusters
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Loosely Coupled Clusters
Network of independent computers
Each has private memory and OS
Connected using I/O system
E.g., Ethernet/switch, Internet
Suitable for applications with independent tasks
Web servers, databases, simulations, …
High availability, scalable, affordable
Problems
Administration cost (prefer virtual machines)
Low interconnect bandwidth
c.f. processor/memory bandwidth on an SMP
Chapter 6 — Parallel Processors from Client to Cloud — 54
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Sum Reduction (Again)
Sum 100,000 on 100 processors
First distribute 100 numbers to each
The do partial sums
sum = 0; for (i = 0; i<1000; i = i + 1) sum = sum + AN[i];
Reduction
Half the processors send, other half receive and add
The quarter send, quarter receive and add, …
Chapter 6 — Parallel Processors from Client to Cloud — 55
Chapter 7 — Multicores, Multiprocessors, and Clusters

56. Example: Sum Reduction
Morgan Kaufmann Publishers
1 July, 2019
Example: Sum Reduction
half = 100;
Repeat /* parallel */
synch();
if (half%2 != 0 && Pn == 0)
sum[0] = sum[0] + sum[half-1];
/* Conditional sum needed when half is odd;
Processor0 gets missing element */
half = half/2; /* dividing line on who sums */
if (Pn < half) sum[Pn] = sum[Pn] + sum[Pn+half];
until (half == 1);
Chapter 6 — Parallel Processors from Client to Cloud — 56
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Sum Reduction (Again)
Given send() and receive() operations
limit = 100; half = 100;/* 100 processors */ repeat half = (half+1)/2; /* send vs. receive dividing line */ if (Pn >= half && Pn < limit) send(Pn - half, sum); if (Pn < (limit/2)) sum = sum + receive(); limit = half; /* upper limit of senders */ until (half == 1); /* exit with final sum */
Send/receive also provide synchronization
Assumes send/receive take similar time to addition
Chapter 6 — Parallel Processors from Client to Cloud — 57
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Grid Computing
Separate computers interconnected by long-haul networks
E.g., Internet connections
Work units farmed out, results sent back
Can make use of idle time on PCs
E.g., World Community Grid
Chapter 6 — Parallel Processors from Client to Cloud — 58
Chapter 7 — Multicores, Multiprocessors, and Clusters

59. Interconnection Networks (SKIP!)
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Interconnection Networks (SKIP!)
Network topologies
Arrangements of processors, switches, and links
§6.8 Introduction to Multiprocessor Network Topologies
Bus
Ring
N-cube (N = 3)
2D Mesh
Fully connected
Chapter 6 — Parallel Processors from Client to Cloud — 59
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Multistage Networks
Chapter 6 — Parallel Processors from Client to Cloud — 60
Chapter 7 — Multicores, Multiprocessors, and Clusters

61. Network Characteristics
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Network Characteristics
Performance
Latency per message (unloaded network)
Throughput
Link bandwidth
Total network bandwidth
Bisection bandwidth
Congestion delays (depending on traffic)
Cost
Power
Routability in silicon
Chapter 6 — Parallel Processors from Client to Cloud — 61
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Parallel Benchmarks
Linpack: matrix linear algebra
SPECrate: parallel run of SPEC CPU programs
Job-level parallelism
SPLASH: Stanford Parallel Applications for Shared Memory
Mix of kernels and applications, strong scaling
NAS (NASA Advanced Supercomputing) suite
computational fluid dynamics kernels
PARSEC (Princeton Application Repository for Shared Memory Computers) suite
Multithreaded applications using Pthreads and OpenMP
§6.10 Multiprocessor Benchmarks and Performance Models
Chapter 6 — Parallel Processors from Client to Cloud — 62
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Code or Applications?
Traditional benchmarks
Fixed code and data sets
Parallel programming is evolving
Should algorithms, programming languages, and tools be part of the system?
Compare systems, provided they implement a given application
E.g., Linpack, Berkeley Design Patterns
Would foster innovation in approaches to parallelism
Chapter 6 — Parallel Processors from Client to Cloud — 63
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Modeling Performance
Assume performance metric of interest is achievable GFLOPs/sec
Measured using computational kernels from Berkeley Design Patterns
Arithmetic intensity of a kernel
FLOPs per byte of memory accessed
For a given computer, determine
Peak GFLOPS (from data sheet)
Peak memory bytes/sec (using Stream benchmark)
Chapter 6 — Parallel Processors from Client to Cloud — 64
Chapter 7 — Multicores, Multiprocessors, and Clusters

65. Roofline Diagram (SKIP!)
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Roofline Diagram (SKIP!)
Attainable GPLOPs/sec
= Max ( Peak Memory BW × Arithmetic Intensity, Peak FP Performance )
Chapter 6 — Parallel Processors from Client to Cloud — 65
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Comparing Systems
Example: Opteron X2 vs. Opteron X4
2-core vs. 4-core, 2× FP performance/core, 2.2GHz vs. 2.3GHz
Same memory system
To get higher performance on X4 than X2
Need high arithmetic intensity
Or working set must fit in X4’s 2MB L-3 cache
Chapter 6 — Parallel Processors from Client to Cloud — 66
Chapter 7 — Multicores, Multiprocessors, and Clusters

67. Optimizing Performance
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Optimizing Performance
Optimize FP performance
Balance adds & multiplies
Improve superscalar ILP and use of SIMD instructions
Optimize memory usage
Software prefetch
Avoid load stalls
Memory affinity
Avoid non-local data accesses
Chapter 6 — Parallel Processors from Client to Cloud — 67
Chapter 7 — Multicores, Multiprocessors, and Clusters

68. Optimizing Performance
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Optimizing Performance
Choice of optimization depends on arithmetic intensity of code
Arithmetic intensity is not always fixed
May scale with problem size
Caching reduces memory accesses
Increases arithmetic intensity
Chapter 6 — Parallel Processors from Client to Cloud — 68
Chapter 7 — Multicores, Multiprocessors, and Clusters

69. Rooflines
Chapter 6 — Parallel Processors from Client to Cloud — 69

70. Benchmarks
Chapter 6 — Parallel Processors from Client to Cloud — 70

71. Performance Summary GPU (480) has 4.4 X the memory bandwidth
Benefits memory bound kernels
GPU has 13.1 X the single precision throughout, 2.5 X the double precision throughput
Benefits FP compute bound kernels
CPU cache prevents some kernels from becoming memory bound when they otherwise would on GPU
GPUs offer scatter-gather, which assists with kernels with strided data
Lack of synchronization and memory consistency support on GPU limits performance for some kernels
Chapter 6 — Parallel Processors from Client to Cloud — 71

72. Multi-threading DGEMM
Use OpenMP:
void dgemm (int n, double* A, double* B, double* C) {
#pragma omp parallel for
for ( int sj = 0; sj < n; sj += BLOCKSIZE )
for ( int si = 0; si < n; si += BLOCKSIZE )
for ( int sk = 0; sk < n; sk += BLOCKSIZE )
do_block(n, si, sj, sk, A, B, C); }
§6.12 Going Faster: Multiple Processors and Matrix Multiply
Chapter 6 — Parallel Processors from Client to Cloud — 72

73. Multithreaded DGEMM
Chapter 6 — Parallel Processors from Client to Cloud — 73

74. Multithreaded DGEMM
Chapter 6 — Parallel Processors from Client to Cloud — 74

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Fallacies
Amdahl’s Law doesn’t apply to parallel computers
Since we can achieve linear speedup
But only on applications with weak scaling
Peak performance tracks observed performance
Marketers like this approach!
But compare Xeon with others in example
Need to be aware of bottlenecks
§6.13 Fallacies and Pitfalls
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Chapter 7 — Multicores, Multiprocessors, and Clusters

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Pitfalls
Not developing the software to take account of a multiprocessor architecture
Example: using a single lock for a shared composite resource
Serializes accesses, even if they could be done in parallel
Use finer-granularity locking
Chapter 6 — Parallel Processors from Client to Cloud — 76
Chapter 7 — Multicores, Multiprocessors, and Clusters

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Concluding Remarks
Goal: higher performance by using multiple processors
Difficulties
Developing parallel software
Devising appropriate architectures
SaaS importance is growing and clusters are a good match
Performance per dollar and performance per Joule drive both mobile and WSC
§6.14 Concluding Remarks
Chapter 6 — Parallel Processors from Client to Cloud — 77
Chapter 7 — Multicores, Multiprocessors, and Clusters

78. Concluding Remarks (con’t)
SIMD and vector operations match multimedia applications and are easy to program
Chapter 6 — Parallel Processors from Client to Cloud — 78