1. Chapter 8 Memory Management
Background
Swapping
Contiguous Allocation
Segmentation
Paging
Structure of the Page Table
Example

2. 8.1 Background: Addressing Requirements for a Process
For relocation, OS must know the location of program (instructions, data) and its PCB

3. 8.1 Background
基本觀念
Program must be brought (from disk) into memory and placed within a process for it to be run
Main memory and registers are only storage CPU can access directly
Memory unit only sees a stream of addresses + read requests, or address + data and write requests
Register access in one CPU clock (or less)
Main memory can take many cycles, causing a stall
Cache sits between main memory and CPU registers
Protection of memory required to ensure correct operation

4. 8.1 Background: Basic Hardware
Protect whole OS from access by user programs
Add two registers to determine the range of legal addresses for a program
Base register – holds the smallest legal physical memory address
Limit register – size of the range
Memory outside the defined range is protected
A base and limit register define a logical address space

5. Figure 8.2: Hardware address protection with base and limit registers
Base and limit registers can be loaded by only the OS, using a special privileged instruction
OS in monitor mode has unrestricted access to both monitor and users’ memory

6. User programs go through several steps before being run
8.1 Background
Program must be brought into memory and placed within a process for it to be run
Input queue
Collection of processes on the disk that are waiting to be brought into memory to run the program
User programs go through several steps before being run

7. 8.1 Background: Binding of Instructions and Data to Memory
Multistep processing of a user program

8. 8.1 Background: Binding of Instructions and Data to Memory
Address binding of instructions and data to memory addresses can happen at three stages
Compile time: If memory location is known beforehand, absolute code can be generated; must recompile code if starting location changes
Load time: Must generate relocatable code if memory location is not known at compile time
Execution time: Binding is delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address mapping (e.g., base and limit registers)

9. 8.1 Background: Address Binding -- Compile Time
Program is written in symbolic code
Compiler translates symbolic code into absolute code
If starting location changes  recompile
Example: MS DOS .COM format binary

10. 8.1 Background: Address Binding -- Load Time
Compiler translates symbolic code into relocatable (可重新定居的) code
If starting location changes  reload the code

11. 8.1 Background: Address Binding -- Execution Time
Compiler translates symbolic code into logical-address code
Special hardware (Memory Management Unit, MMU) is needed
Most general-purpose OS use this method

12. 8.1 Background: Logical vs. Physical Address Space
The concept of a logical address space bound to a separate physical address space is central to memory management
Logical address – generated by the CPU (also known as virtual address)
Physical address – address seen by the memory unit
Logical and physical addresses are the same in compile-time and load-time address-binding schemes
Logical and physical addresses differ in execution-time address-binding scheme

13. Dynamic Relocation Using a Relocation Register
(Memory Management Unit)
Hardware device that maps virtual to physical address
In MMU scheme, the value in the relocation register is added to every address
generated by a user process at the time it is sent to memory
User program deals with logical addresses; never sees the real physical addresses

14. 8.1 Background: Dynamic Loading
Routine is not loaded until it is called
All routines are kept on disk in a relocatable load format
To call another routine, the calling routine first checks to see if the other routine has been loaded
If not, the relocatable linking loader is called to load the desired routine into memory
Better memory-space utilization
Unused routine is never loaded
Useful when large amounts of code are needed to handle infrequently occurring cases
No special support from the OS is required
Implemented through program design

15. 8.1 Background: Dynamic Linking
Linking is postponed till execution time
Small piece of code, stub
Indicates how to locate the appropriate memory-resident library routine or to load the library if the routine is not already present
Stub replaces itself with the address of the routine, and executes the routine
All processes using the routine execute only one copy of the library code
Unlike dynamic loading, OS is required to check if routine is in another processes’ memory address
 Memory protection

16. 8.2 Swapping
A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution
Backing store
Fast disk large enough to accommodate copies of all memory images for all users
Must provide direct access to these memory images
Roll out, roll in
Swapping variant is used for priority-based scheduling algorithms
Lower-priority process is swapped out so higher-priority process can be loaded and executed

17. Schematic View of Swapping

18. Major part of swap time is transfer time
8.2 Swapping
Major part of swap time is transfer time
Total transfer time is directly proportional to the amount of memory swapped
Modified versions of swapping are found on many systems
例: UNIX, Linux, Windows
Swapping is normally disabled, but would start if many processes were running and were using a threshold amount of memory

19. 8.3 Contiguous Allocation
Main memory is usually divided into two partitions:
Resident OS, usually held in low memory with interrupt vector
User processes in high memory
Single-partition allocation (for memory protection)
Relocation register protects user processes from each other, and from changing OS code/data
Relocation register contains value of smallest physical address
Limit register contains range of logical addresses
Each logical address must be less than the limit register

20. 8.3 Contiguous Allocation: Memory Protection
Dispatcher loads
Hardware support for relocation and limit registers

21. 8.3 Contiguous Allocation: Memory Allocation
Multiple-partition allocation
Hole – block of available memory; holes of various size are scattered throughout memory
When a process arrives, it is allocated memory from a hole large enough to accommodate it
OS maintains information about: a) allocated partitions b) free partitions (hole) OS OS OS OS
process 5
process 5
process 5
process 5
process 9
process 9
process 8
process 10
process 2
process 2
process 2
process 2

22. 8.3 Contiguous Allocation: Memory Allocation
作業系統如何維護可分配的記憶體空間？
Linked list為常見的實作方式
上圖顯示5 processes, 3 holes

23. How to satisfy a request of size n from a list of free holes
8.3 Contiguous Allocation: Memory Allocation ---Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes
First-fit: Allocate the first hole that is big enough
Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole
First-fit and best-fit are better than worst-fit in terms of speed and storage utilization
First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to fragmentation
“1/3 may be unusable”  50-percent rule

24. 8.3 Contiguous Allocation: Fragmentation
Main memory
Allocated partition
Used
Used
Used
Unused
Free (hole)
External fragmentation
Used
Internal fragmentation
Free (hole)
Used

25. 8.3 Contiguous Allocation: Fragmentation
External fragmentation (vs. internal fragmentation)
Total memory space exists to satisfy a request, but it is not contiguous
Compaction
註：compaction意為“原本鬆散的東西壓緊實”

26. 8.3 Contiguous Allocation: Fragmentation
Reduce external fragmentation by compaction
Shuffle memory contents to place all free memory together in one large block
Compaction is possible only if relocation is dynamic, and is done at execution time
I/O problem
Latch job in memory while it is involved in I/O
Do I/O only into OS buffers
Swapping can also be combined with compaction
Roll-out → compaction → roll-in

27. 8.3 Contiguous Allocation: Fragmentation
Different ways to compact memory

28. 8.3 Contiguous Allocation: Fragmentation
Internal fragmentation
Sometimes the overhead to keep track of a hole will be substantially larger than the hole itself
Break the physical memory into fixed-sized blocks and allocate memory in unit of memory blocks
Allocated memory may be slightly larger than requested
This size difference is memory internal to a partition, but is not being used

29. A program is a collection of segments
8.4 Segmentation (分段)
Users prefer to view memory as a collection of variable-sized segments, with no necessary ordering among segments
Segmentation is a memory-management scheme that supports user view of memory
A program is a collection of segments
A segment is a logical unit such as main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays

30. 8.4 Segmentation: User’s View of a Program

31. 8.4 Segmentation: Logical View of Segmentation1 4 2 3 1 2 3 4
user space
physical memory space

32. 8.4 Segmentation: Hardware
Architecture
Logical address <segment-number, offset>
Segment table maps two-dimensional physical addresses. Each table entry has:
base – contains the starting physical address where the segments reside in memory
limit – specifies the length of the segment
Segment table = array of base-limit register pairs
Segment-table base register (STBR) points to the segment table’s location in memory
Segment-table length register (STLR) indicates number of segments used by a program
Segment number s is legal if s < STLR

33. 8.4 Segmentation: Hardware

34. 8.4 Segmentation: Hardware (Example)

35. 8.4 Segmentation: Protection and Sharing
With each entry in segment table associate:
Validation bit = 0  illegal segment
Read/write/execute privileges
Protection bits associated with segments
Sharing (code sharing at segment level)
Segment-table entries of two different processes point to the same physical locations
When shared code segments contain direct references to themselves, all sharing process must define the shared code segment to have the same segment number

36. 8.4 Segmentation: Protection and Sharing

37. 8.5 Paging (分頁)
A scheme that permits the physical address space of a process to be noncontiguous
Process is allocated physical memory whenever memory is available
Divide physical memory into fixed-sized blocks called frames (size 2n)
64位元CPU可定址264記憶體空間?
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size n pages, need to find n free frames and load program

38. 8.5 Paging: Address Translation Scheme
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which contains base address of each page in physical memory
Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit
page number
page offset p d
m - n n
Logical address space 2m and page size 2n

39. Paging Example
Page size = 2n, 512 bytes~1GB per page

40. Linux環境取得分頁大小資訊 舉一反三：Windows10哪一個組態檔可設定分頁大小？設大設小有差別？
getconf: get configuration 取得系統組態資訊
舉一反三：Windows10哪一個組態檔可設定分頁大小？設大設小有差別？

41. Paging example for a 32-byte memory with 4-byte pages (n=2, m=4)
page number
page offset p d
m - n n
Logical address space 2m , page size 2n

42. 8.5 Paging: Fragmentation
Calculating internal fragmentation
Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2, ,086 = 962 bytes
Worst case fragmentation = 1 frame – 1 byte
On average fragmentation = 1 / 2 frame size
So small frame sizes desirable?
But each page table entry takes memory to track
Page sizes growing over time
Process view and physical memory now very different

43. 8.5 Paging: Free Frames (Frame Table Maintained by the OS)
Before allocation
After allocation

44. 8.5 Paging: Hardware Support
Implementation of the page table
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PRLR) indicates size of the page table
In this scheme every data/instruction access requires two memory accesses, one for the page table and one for the data/instruction
The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)

45. 8.5 Paging: Hardware Support
Associative memory – cache $$$
Can be < 10% of memory access time
Parallel search
Address translation (A’, A’’)
If A’ is in associative register, get frame# out
Otherwise get frame# from page table in memory
Context switch causes flushing of TLB
Page #
Frame #

46. 8.5 Paging: Paging Hardware with TLB

47. 8.5 Paging: Paging Hardware With TLB
Effective memory-access time
Associative lookup =  time unit
Assume memory cycle time is 1 μs
Hit ratio ()
Percentage of times that a page number is found in the associative registers; ratio related to number of associative registers
Effective access time = ( +1)+(+2)(1–) = 2+– 例：
Hit ratio = 80%
TLB access time = 20 nanosec.
Memory access time = 100 nanosec.
Effective memory-access time = 80% × (20+100) % × ( )

48. 8.5 Paging: Memory Protection
Memory protection by associating protection bit with each frame
Read-write/read-only bit per page table entry (set by the OS), plus
Valid-invalid bit attached to each entry in the page table
“valid” indicates that the associated page is in the process’ logical address space, ∴ a legal page
“invalid” indicates that the page is not in the process’ logical address space
OS sets this bit for each page to allow/disallow accesses to that page

49. 8.5 Paging: Memory Protection

50. 8.5 Paging: Shared Pages Shared code Private code and data
One copy of read-only (re-entrant) code shared among processes
例: text editors, compilers
Reentrant code is non-self-modifying, i.e., never changes during execution time
Shared code must appear in same location in the logical address space of all processes
Private code and data
Each process keeps a separate copy of the code and data
Pages for the private code and data can appear anywhere in the logical address space

51. Shared Pages圖例 (Figure 8.16)

52. 8.6 Paging: Page Table Structures
Most modern computer systems support a very large logical address space (232 to 264)
The page table becomes very large
例: a 32-bit logical address space and page size = 4 K (212), we have 1 million entries
Hierarchical paging
Break up the logical address space into multiple page tables
A simple technique is a two-level page table
Hashed page tables
Inverted page tables

53. 8.6 Paging: Page Table Structures (Hierarchical Paging)
Logical address space = 232
Page size = 4 KB = 212 B
Number of pages = 232/212 = 220
Size of page table = 220 x page entry
Assume page entry = 4 bytes
Each process’ page table = 4 MB physical-address space
4 KB page size vs. 4 MB page table  larger than a page
The page table is itself paged!
The number of required pages by the table = 210 pages
Solution: Divide the page table into smaller pieces
Page 1
232
Page 220

54. 8.6 Paging: Page Table Structures (Hierarchical Paging)
Two-level paging
A logical address (on 32-bit machine with 4K page size) is divided into:
a page number consisting of 20 bits
a page offset consisting of 12 bits
Since the page table is paged, the page number is further divided into:
a 10-bit page number
a 10-bit page offset
Thus, a logical address is where p1 is an index into the outer page table, and p2 is the displacement within the page of the outer page table
page number
page offset p1 p2 d 10 10 12

55. 8.6 Paging: Page Table Structures (Hierarchical Paging)
Two-level paging example
210x word size = 210 x 4 = 4 KB = 1 page
Each page can hold 4 KB / 4 page entries = 1 K

56. 8.6 Paging: Page Table Structures (Hierarchical Paging)
Address-translation scheme for a two-level 32-bit paging architecture

57. 8.6 Paging: Page Table Structures (Hierarchical Paging)
Three-level paging

58. 8.6 Paging: Page Table Structures (Hashed Page Tables)
Common scheme to handle address spaces > 32 bits
Virtual page number is hashed into a page table
Each entry in the hash table contains a linked list of elements that hash to the same location
Each element is composed of 3 fields
Virtual page number, value of the mapped page frame, pointer to the next element in the linked list
Virtual page numbers are compared in this linked list searching for a match
If a match is found, the corresponding physical frame is extracted

59. 8.6 Paging: Page Table Structures (Hashed Page Tables)

60. 補充：Hash
A hash function maps data of arbitrary (任意) size to data of a fixed size
發生collision需有額外的處理機制
雜湊函數範例
雜湊函數把訊息或資料壓縮成摘要，使得資料量變小，把資料的格式固定下來。該函式把資料打亂混合，建立雜湊值。雜湊函數在資訊安全(數位簽章)領域廣為使用

61. 8.6 Paging: Page Table Structures (Inverted Page Table)
To solve the problem with one page table per process  large memory for all tables
One entry for each frame
Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page
Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs
Inverted page table sorted by physical address
Lookups occur in logical address
Use hash table to limit the search to one (or at most a few) page-table entries

62. 8.6 Paging: Page Table Structures (Inverted Page Table)
比較此圖與Figure 8.10的差異
<process-id, page-number, offset>
以<pid, page-number>作為查表的依據
整個系統僅保有一份分頁表，被所有程序共用

63. 8.6.4 Oracle SPARC Solaris
不列入考試範圍

64. 8.7 Example
不列入考試範圍