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Day 26: November 10, 2010 Memory Periphery

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Presentation on theme: "Day 26: November 10, 2010 Memory Periphery"— Presentation transcript:

1 Day 26: November 10, 2010 Memory Periphery
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 26: November 10, 2010 Memory Periphery Penn ESE370 Fall DeHon

2 Today Decode Sensing Penn ESE370 Fall DeHon

3 Memory Bank Penn ESE370 Fall DeHon

4 Row Select Logically a big AND
May include an enable for timing in synchronous Penn ESE370 Fall DeHon

5 Row Select How can we do better? Area Delay
Match to pitch of memory row Penn ESE370 Fall DeHon

6 Row Select Compute inversions outside array
Just AND appropriate line (bit or /bit) Penn ESE370 Fall DeHon

7 Row Select Share common terms Multi-level decode
Penn ESE370 Fall DeHon

8 Row Select Same number of lines Half as many AND inputs
Penn ESE370 Fall DeHon

9 Row Select: Precharge NAND
Penn ESE370 Fall DeHon

10 Sensing Penn ESE370 Fall DeHon

11 Differential Sense Amp
Penn ESE370 Fall DeHon

12 Differential Sense Amp
Penn ESE370 Fall DeHon

13 “Inverter” Penn ESE370 Fall DeHon

14 “Inverter” Input high Input low Ratioed like grounded P
Pulls itself up Until Vdd-VTP Penn ESE370 Fall DeHon

15 DC Transfer Function Penn ESE370 Fall DeHon

16 Differential Sense Amp
Penn ESE370 Fall DeHon

17 Differential Sense Amp
“Inverter” output controls PMOS for second inverter Sets PMOS operating point current Penn ESE370 Fall DeHon

18 Differential Sense Amp
View: Current mirror Biases where inverter operating Penn ESE370 Fall DeHon

19 Differential Sense Amp
View: adjusting the pullup load resistance Changing the trip point for “inverter” Penn ESE370 Fall DeHon

20 DC Transfer /in with in=0.5V
Penn ESE370 Fall DeHon

21 DC Transfer Various in Penn ESE370 Fall DeHon

22 After Inverter Penn ESE370 Fall DeHon

23 Connect to Column Equalize lines during precharge
Penn ESE370 Fall DeHon

24 Singled-Ended Read Penn ESE370 Fall DeHon

25 5T SRAM Penn ESE370 Fall DeHon

26 Single Ended Need reference to compare against
Want to look just like bit line Equalize with bit line Penn ESE370 Fall DeHon

27 Split Bit Line Split bit-line in half Precharge/equalize both
Word in only one half Only it switches Amplify difference Penn ESE370 Fall DeHon

28 Open Bit Line Architecture
For 1T DRAM Add dummy cells Charge dummy cells to Vdd/2 “read” dummy in reference half Penn ESE370 Fall DeHon

29 Memory Bank Penn ESE370 Fall DeHon

30 Admin Have memory cell Andrew office hours Wednesday and Thursday
Add drivers and amps Andrew office hours Wednesday and Thursday Penn ESE370 Fall DeHon

31 Idea Minimize area of repeated cell Compensate with periphery
Amplification (restoration) Match periphery pitch to cell row/column Decode Sensing Writer Drivers Penn ESE370 Fall DeHon


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