1. COMPUTER ORGANIZATION AND ARCHITECTURE
15EM2001
COMPUTER ORGANIZATION AND ARCHITECTURE
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2. Introduction to RISC
Since the development of the stored program computer around 1950, there are few innovations in the area of computer organization and architecture. Some of the major developments are:
The Family Concept (1964)
Microprogrammed Control Unit (1951)
Cache Memory (1968)
Pipelining
Multiple Processor
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3. The computer designers intend to reduce this gap (i. e
The computer designers intend to reduce this gap (i.e., semantic and high level programming languages) and include large instruction set, more addressing mode and various HLL statements implemented in hardware.
As a result the instruction set becomes complex. Such complex instruction sets are intended to:
Ease the task of the compiler writer.
Improve execution efficiency, because complex sequences of operations can be implemented in microcode.
Provide support for even more complex and sophisticated HLLs.
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4. Complex Instruction Set Computer (CISC).
The instruction execution characteristics involves the following aspects of computation:
Operation Performed
Operand Used
Execution sequencing
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5. Reduced Instruction Set Computer (RISC).
A large number of general purpose registers, or the use of compiler technology to optimize register usage.
A limited and simple instruction set.
An emphasis on optimizing the instruction pipeline
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6. Characteristics of some CISCs, RISCs and Superscalar Processors:
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7. Comparison of RISC & CISC
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8. Characteristics of Reduced Instruction Set Architecture (RISC)
Certain common characteristics are :
One instruction per cycle.
Register–to–register operations.
Simple addressing modes.
Simple instruction formats.
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9. Design Issues of RISC 1. The use of a large register file:
Two basic approaches are possible, one is based on software and the other on hardware.
The software approach
The hardware approach
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10. Design Issues of RISC (Cont’d…..)
2. Register Window:
The use of a large set of registers should decrease the need to access memory. The design task is to organize the registers in such a way that this goal is realized.
Thus the variables that are used in a program can be categorized as follows :
Global variables
Local variables
Passed parameters
Returned variable
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11. Design Issues of RISC (Cont’d…..)
2. Register Window: (Cont’d….)
The register window is divided into three fixed-size areas.
Parameter registers: hold parameters passed down from the procedure that called the current procedure and hold results to be passed back up.
Local registers are used for local variables.
Temporary registers are used to exchange parameters and results with the next lower level (procedure called by current procedure)
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12. Design Issues of RISC (Cont’d…..)
2. Register Window: (Cont’d….)
Overlapping Register Windows
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13. Design Issues of RISC (Cont’d…..)
3. Compiler based Register Optimization:
To optimize the use of registers, the approach taken is as follows:
Each program quantity that is a candidate for residing in a register is assigned to a symbolic or virtual register.
The compiler then maps the unlimited number of symbolic registers into a fixed number of real registers.
Symbolic registers whose usage does not overlap can share the same real register.
If in a particular portion of the program, there are more quantities to deal with than real registers, then some of the quantities are assigned to the memory location.
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14. Design Issues of RISC (Cont’d…..)
3. Compiler based Register Optimization: (Cont’d….)
The technique most commonly used in RISC compiler is known as graph colouring.
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15. Large Register file versus cache
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16. Parallel processing
Parallel processing may occur in the instruction stream, in the data stream, or in both. Flynn's classification divides computers into four major groups as follows:
Single instruction stream, single data stream (SISD)
Single instruction stream, multiple data stream (SIMD)
Multiple instruction stream, single data stream (MISD)
Multiple instruction stream, multiple data stream (MIMD)
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17. Introduction to pipelining
Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub-process being executed in a special dedicated segment that operates concurrently with all other segments.
Conventional Sequential Execution
Pipelined Execution
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18. Introduction to pipelining: (Cont’d…..)
Example of pipelining
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19. Introduction to pipelining: (Cont’d…..)
Decomposition of the instruction execution:
Fetch Instruction (FI)
Decode Instruction (DI)
Calculate Operand (CO)
Fetch Operands(FO)
Execute Instruction (EI)
Write Operand(WO)
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20. Introduction to pipelining: (Cont’d…..)
Timing Diagram for Instruction Pipeline Operation
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21. Four Stage Pipeline
F: Fetch, Read the instruction from the memory D: Decode, decode the instruction and fetch the source operand (S) O: Operate, perform the operation W: Write, store the result in the destination location.
Timing diagram for 4- stage instruction pipeline
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22. Instruction Execution in a Four Stage Pipeline
Flow-chart
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23. Design Issues of Pipeline
The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline. The cycle time can be determined as: Where,
= time delay of the circuitry in the ith stage of the pipeline
= maximum stage delay (delay through stage which experiences the largest delay)
= number of stages in the instruction pipeline
= time delay of a latch, needed to advance signals and data from one stage to the next
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24. Design Issues of Pipeline: (Cont’d….)
Let Tk,n be the total time required for a pipeline with k stages to execute n instructions. Then,
A total of k cycles are required to complete the execution of the first instruction, and the remaining n-1 instructions require n-1 cycles.
consider a processor with equivalent functions but no pipeline, and assume that the instruction cycle time is
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25. Design Issues of Pipeline: (Cont’d….)
The speedup factor for the instruction pipeline compared to execution without the pipeline is defined as
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26. Pipeline Hazards
A pipeline hazard occurs when the pipeline, or some portion of the pipeline, must stall because conditions do not permit continued execution. Such a pipeline stall is also referred to as a pipeline bubble.
There are three types of hazards:
Resource Hazards or Structural Hazards
Data Hazards
Control Hazards or Branch Hazards
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27. Resource Hazards Example of Resource Hazard
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28. Data Hazards Read after write (RAW), or true dependency
Write after read (WAR), or anti-dependency
Write after write (WAW), or output dependency.
Example of Data Hazard
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29. Control Hazards Dealing with Branches Multiple streams
Pre-fetch branch target
Loop buffer
Branch prediction
Delayed branch
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30. Control Hazards
The Effect of a Conditional Branch on Instruction Pipeline Operation
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31. Arithmetic Pipeline
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32. Floating point adder Numerical Example:
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33. Attached Array Processor
An attached array processor is an auxiliary processor attached to a general-purpose computer. It is intended to improve the performance of the host computer in specific task.
Attached array processor with host computer
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34. SIMD array processor SIMD array processor organization
An Single Input Multi Data (SIMD) array processor is a computer with multiple processing units operating in parallel.
SIMD array processor organization
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35. Vector Processing
The following are representative application areas where vector processing is of the utmost importance.
Long-range weather forecasting
Petroleum explorations
Seismic data analysis
Medical diagnosis
Aerodynamics and space flight simulations
Artificial intelligence and expert systems
Mapping the human genome
Image processing
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36. Instruction level parallelism
General Superscalar Organization
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37. Fundamental limitations to parallelism
True data dependency
Procedural dependency
Resource conflicts
Output dependency
Anti-dependency
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