1. Alternative datapath (book): Multiple Cycle Datapath
Miminizes Hardware: 1 memory, 1 adder
PCWr
PCWrCond
PCSrc
Zero
IorD
MemWr
IRWr
RegDst
RegWr
ALUSelA 1 32 32
Mux PC
Mux 1 32
Instruction Reg
Zero Rs
Mux 1 Ra 32
RAdr 5 32 Rt
ALU Out 32 Rb
busA A 32
Ideal
Memory 32
ALU 5
Reg File
Mux 1 Rt 4 Rw 32
WrAdr 32 B 32 32 Rd 32 1
Din
Dout
Mem Data Reg
busW
busB 32 2
ALU
Control
Putting it all together, here it is: the multiple cycle datapath we set out to built.
+1 = 47 min. (Y:47)
Mux 1 3
<< 2
Extend
Imm 16 32
ALUOp
ExtOp
MemtoReg
ALUSelB
3/8/99
©UCB Spring 1999

2. Finite State Machine (FSM) Spec
IR <= MEM[PC]
PC <= PC + 4
“instruction fetch”
0000
ALUout <= PC +SX
“decode”
Q: How improve
to do something in
state 0001?
0001 LW
BEQ
R-type
ORi SW
ALUout <= A fun B
ALUout <= A or ZX
ALUout <= A + SX
ALUout <= A + SX
If A = B then PC <= ALUout
Execute
0100
0110
1000
1011
0010
M <= MEM[ALUout]
Memory
MEM[ALUout] <= B
1001
1100
R[rd] <= ALUout
R[rt] <= ALUout
R[rt] <= M
Write-back
0101
0111
1010
3/8/99
©UCB Spring 1999

3. 4) Legend of Fields and Symbolic Names
Field Name Values for Field Function of Field with Specific Value ALU Add ALU adds Subt. ALU subtracts Func code ALU does function code Or ALU does logical OR SRC1 PC 1st ALU input = PC rs 1st ALU input = Reg[rs] SRC2 4 2nd ALU input = 4 Extend 2nd ALU input = sign ext. IR[15-0] Extend0 2nd ALU input = zero ext. IR[15-0] Extshft 2nd ALU input = sign ex., sl IR[15-0] rt 2nd ALU input = Reg[rt] destination rd ALU Reg[rd] = ALUout rt ALU Reg[rt] = ALUout rt Mem Reg[rt] = Mem Memory Read PC Read memory using PC Read ALU Read memory using ALU output Write ALU Write memory using ALU output Memory register IR IR = Mem PC write ALU PC = ALU ALUoutCond IF ALU Zero then PC = ALUout Sequencing Seq Go to sequential µinstruction Fetch Go to the first microinstruction Dispatch Dispatch using ROM.
Note: can specify combinations of fields that may not be possible or not work properly given the datapath (e.g., ALU operand and write register in single cycle)
3/8/99
©UCB Spring 1999

4. Microprogram it yourself!
Label ALU SRC1 SRC2 ALU Dest. Memory Mem. Reg. PC Write Sequencing
Fetch: Add PC 4 Read PC IR ALU Seq
1) Do two microinstructions on slide
2) Refer to the FSD each time first to see what should be done
3) look up the values in the fields each time to see what to do
4) Probably want multiple slides
5) Come out of presentation mode so that can edit the result on the screen
Advantages of microprogramming:
ease of change (show edit step)
3/8/99
©UCB Spring 1999

5. 1&2) Start with list of control signals, grouped into fields
Signal name Effect when deasserted Effect when asserted ALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs] RegWrite None Reg. is written MemtoReg Reg. write data input = ALU Reg. write data input = memory RegDst Reg. dest. no. = rt Reg. dest. no. = rd MemRead None Memory at address is read, MDR <= Mem[addr] MemWrite None Memory at address is written IorD Memory address = PC Memory address = S IRWrite None IR <= Memory PCWrite None PC <= PCSource PCWriteCond None IF ALUzero then PC <= PCSource PCSource PCSource = ALU PCSource = ALUout
Single Bit Control
Signal name Value Effect ALUOp 00 ALU adds ALU subtracts ALU does function code 11 ALU does logical OR ALUSelB 000 2nd ALU input = Reg[rt] nd ALU input = nd ALU input = sign extended IR[15-0] nd ALU input = sign extended, shift left 2 IR[15-0] nd ALU input = zero extended IR[15-0]
Multiple Bit Control
3/8/99
©UCB Spring 1999