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Impact of Technology Scaling
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Goals of Technology Scaling
Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a transistor has to be reduced But also want to be faster, smaller, lower power
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Technology Scaling Goals of scaling the dimensions by 30%:
Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power 43% increase in frequency Die size used to increase by 14% per generation Technology generation spans 2-3 years
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Technology Generations
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Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors 186 177 171 160 130 106 90 Max mP power [W] 1.4 1.2 6-7 180 1999 1.7 2000 14.9 -3.6 11-3 3.5-2 Max frequency [GHz],Local-Global 2.5 2.3 2.1 2.4 2.0 Bat. power [W] 10 9-10 9 8 7 Wiring levels Supply [V] 30 40 60 Technology node [nm] 2014 2011 2008 2004 2001 Year of Introduction Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
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Technology Evolution (1999)
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ITRS Technology Roadmap Acceleration Continues
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Technology Scaling (1) Minimum Feature Size
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Number of components per chip
Technology Scaling (2) Number of components per chip
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Technology Scaling (3) Propagation Delay tp decreases by 13%/year
50% every 5 years! Propagation Delay
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Technology Scaling (4) From Kuroda
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Technology Scaling Models
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Scaling Relationships for Long Channel Devices
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Transistor Scaling (velocity-saturated devices)
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mProcessor Scaling P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
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mProcessor Power P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
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mProcessor Performance
P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
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2010 Outlook Performance 2X/16 months Size Power
1 TIP (terra instructions/s) 30 GHz clock Size No of transistors: 2 Billion Die: 40*40 mm Power 10kW!! Leakage: 1/3 active Power P.Gelsinger: mProcessors for the New Millenium, ISSCC 2001
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SPICE Models
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MOSFET Modeling Basic approaches: Physical Empirical
based on device models extracted from process parameters Empirical based on curve fitting from measured data curves are fitted to measured device char.
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Spice Models First generation – Level 1, 2, 3 (Obsolete)
Physical or semi-empirical analytical models with geometry in model equations Second generation – Level 13 (BSIM), 28 (MetaMOS), 39 (BSIM2) Emphasis to circuit simulation, bins, works for submicron, down to 0.5mm Third generation – Level 49 (BSIM3v3), 55 (EKV) Simplification, deep-submicron, low voltages BSIM3v3 is a current industry standard, Getting complicated
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BSIM3V3 SPICE Transistors Parameters
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SPICE Transistors Parameters
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BSIM3v3 Model Over 80 parameters *model = bsim3v3
*Berkeley Spice Compatibility * Lmin= .35 Lmax= 20 Wmin= .6 Wmax= 20 .model N1 NMOS +Level= 8 +Tnom=27.0 +Nch= 2.498E+17 Tox=9E-09 Xj= E-07 +Lint=9.36e-8 Wint=1.47e-7 +Vth0= K1= .756 K2= -3.83e-2 K3= Dvt0= Dvt1= Dvt2=-9.17e-2 +Nlx= E-08 W0= 1.163e-6 +K3b= Vsat= Ua= 6.47e-9 Ub= 4.23e-18 Uc= E-11 +Rdsw= 650 U0= wr=1 +A0= Ags=.1 B0=0.546 B1= 1 + Dwg = -6.0E-09 Dwb = -3.56E-09 Prwb = Keta= E-02 A1= E-02 A2= .9 +Voff= E-02 NFactor= Cit= E-04 +Cdsc= E-05 +Cdscb= 0 Dvt0w = 0 Dvt1w = 0 Dvt2w = 0 + Cdscd = 0 Prwg = 0 +Eta0= E-02 Etab= E-03 +Dsub= Pclm= Pdiblc1= E-03 Pdiblc2= E-03 +Drout= Pscbe1= Pscbe2= 5E-09 Pdiblcb = Pvag= 0 delta= Wl = 0 Ww = E-09 Wwl = 0 + Wln = 0 Wwn = Ll = E-10 + Lw = 0 Lwl = 0 Lln = Lwn = 0 +kt1=-.3 kt2= At= Ute= Ua1= 3.31E-10 Ub1= 2.61E-19 Uc1= -3.42e-10 +Kt1l=0 Prt=764.3 Over 80 parameters
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Process Variation
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Process Variation
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Process Corner Process Variations: Environment Variation
TT: typical model SS: Slow NMOS, Slow PMOS Model FF: Fast NMOS, Fast PMOS Model SF: Slow NMOS, Fast PMOS Model FS: Fast NMOS, Slow PMOS Model Environment Variation Temperature Supply Voltage
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Simulation Conditions
TT, Nominal temp, Nominal supply – design objective TT, High temp, Min supply – design for SS, High temp, Min supply – sometimes design for FF, Low temp, Max supply – power, supply lines FS, SF, - some logic styles are sensitive…
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