1. Branch Predictor Interface
typedef struct { Bool taken; Addr target; } BPBundle deriving(Bits, Eq); interface BPredictor; method BPBundle prediction(Addr pc); method Action update(Addr pc, Addr target, IType type, Bool taken); endinterface
January 18, 2012

2. Null Branch Prediction
module mkNeverTaken(BPredictor); method BPBundle prediction(Addr pc); return BPBundle{taken: False, target: pc+4}; method update = ?; endmodule
Replaces PC+4 with …
Already implemented in the pipeline
Right most of the time
Why?
January 18, 2012

3. Two-Stage SMIPS Register File PC Decode Execute Inst Data Memory
Epoch
Register File PC fr
Decode
Execute +4
Inst
Memory
Data
Memory
January 18, 2012 3

4. Two-Stage SMIPS + BP Register File PC Decode Execute Data Memory Inst
Epoch
Register File PC fr
Decode
Execute
Branch
Predictor
bpr
Data
Memory
Inst
Memory
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5. Two-Stage SMIPS +BP module mkProc(Proc); Reg#(Addr) pc <- mkRegU;
Reg#(Bool) epoch <- mkRegU;
RFile rf <- mkRFile;
BranchPredictor bpred <- mkNeverTaken;
Memory mem <- mkTwoPortedMemory;
let iMem = mem.iport; let dMem = mem.dport;
PipeReg#(FBundle) fr <- mkPipeReg;
PipeReg#(BPBundle) bpr <- mkPipeReg;
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6. Two-Stage SMIPS +BP rule doProc; BPBundle bp = bpred(pc);
if(fr.notFull && bp.notFull) begin
let inst <- iMem(MemReq{op: Ld, addr: pc,
data: ?});
fr.enq(FBundle{pc: pc, epoch: epoch,
inst: inst});
bpr.enq(bp);
end
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7. Two-Stage SMIPS + BP Addr redirPc = ?; Bool redirPCvalid = False;
if(fr.notEmpty) begin
let frpc = fr.first.pc;
let inst = fr.first.inst;
if(fr.first.epoch==epoch) begin
let dInst = decode(inst);
Data rVal1 = rf.rd1(dInst.rSrc1);
Data rVal2 = rf.rd2(dInst.rSrc2);
let eInst = exec(dInst, rVal1, rVal2, frpc);
if(memType(eInst.iType))
eInst.data <- dMem(MemReq{
op: eInst.iType==Ld ? Ld : St,
addr: eInst.addr, data: eInst.data});
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8. Two-Stage SMIPS +BP if(eInst.brTaken) begin redirPC = eInst.addr;
redirPCvalid = eInst.brTaken != bpr.brTaken;
end
bp.update(bpr.pc, eInst.addr,
eInst.iType, eInst.brTaken);
if(regWriteType(eInst.iType))
rf.wr(eInst.rDst, eInst.data);
fr.deq;
bpr.deq;
end1
pc <= redirPCvalid ? redirPC : bp.target;
epoch <= redirPCvalid ? !epoch : epoch;
endrule endmodule
January 18, 2012