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Variations-Aware Circuit Designs for Microprocessors Marc Pons, Thesis Advisors: Francesc Moll, Jaume Abella Electronic Engineering Department Universitat.

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Presentation on theme: "Variations-Aware Circuit Designs for Microprocessors Marc Pons, Thesis Advisors: Francesc Moll, Jaume Abella Electronic Engineering Department Universitat."— Presentation transcript:

1 Variations-Aware Circuit Designs for Microprocessors Marc Pons, Thesis Advisors: Francesc Moll, Jaume Abella Electronic Engineering Department Universitat Politècnica de Catalunya

2 OUTLINE Integrated Circuits Manufacturing The Need for Regularity
Conclusion 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 2

3 IC MANUFACTURING [ASML]
1st Barcelona Forum on Ph.D. Research in Electronic Engineering 3

4 LITHOGRAPHY LIMITS 1980 1990 2000 2010 2020 10 1 0.1 um [Intel] -nce
WYS is not WYG 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 4

5 RESOLUTION ENHANCEMENT TECHNIQUES
RETs are applied to mitigate process variations However RETs are computationally expensive for large circuits with arbitrary layout patterns RETs are computationally expensive and very time-consuming for large integrated circuits with arbitrary layout patterns

6 DECREASING YIELD [Synopsys]
1st Barcelona Forum on Ph.D. Research in Electronic Engineering 6

7 INCREASING COSTS 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 7

8 DECREASING BENEFITS 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 8

9 DECREASING YIELD Regularity to Rescue [Synopsys]
1st Barcelona Forum on Ph.D. Research in Electronic Engineering 9

10 REGULARITY TODAY TOMORROW [Rabaey]
1st Barcelona Forum on Ph.D. Research in Electronic Engineering 10

11 LAYOUT LAYERS OUR PROPOSAL (REGULARITY) CONVENTIONAL (IRREGULARITY)
1st Barcelona Forum on Ph.D. Research in Electronic Engineering 11

12 ADDER LAYOUTS 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 12

13 CONCLUSION Lithography Process Variations reduce Integrated Circuits Yield We propose to include Regularity in design to mitigate Process Variations We are studying the trade-offs involved

14 Thank you for your attention!
1st Barcelona Forum on Ph.D. Research in Electronic Engineering 14

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