1. Data Concentrator Card and Test System for the CMS ECAL Readout
Presentation Outline
ECAL OD Electronics and Readout Architecture
DCC System
DCC TC System
Test Bench

2. DCC Team Project Manager DCC and DCC-TC Design and Conception
João Varela
DCC and DCC-TC Design and Conception
José C. Da Silva, Nuno Cardoso
Data Simulation, Control and Monitoring Software
Nuno Almeida, Reyes Alemany

3. ECAL Off-Detector Electronics and Readout Architecture
TTS
TTC
RCS
Local Triggers In
Stand alone
Mode
Laser
Partition
TTS copper link
TTC optical link
CCS
(Clock and Control System )
Local copper control link
Local copper
control link
Token Ring
Control Loops
TCC
(Trigger Concentrator Card)
DCC
(Data Concentrator Card)
Regional
Trigger FE
(ON-DETECTOR)
DAQ
Data
DAQ
Data
Trigger
Data
Trigger
Data
SRP
(Selective Readout Processor)
SR Flags

4. ECAL Off-Detector Crates
Endcap Left
Barrel
Endcap Right D C S R O T D C S T R O D C S R O T
x 3
x 8
x 3 D C S T R O
x 2
Barrel
EndCap Left
EndCap Righ
Outer
Inner
Left
Right
Inner
Outer S R P C T C S I A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B
SRP Crate x1

5. DCC Functionality
Opto-Electric conversion and deserialization of the input data streams (70 x 800 MBit/s)
Input data integrity verification
Link status, source id, data block length, word parity bits, L1A and bx numbers.
Input data volume reduction (~20)
Application of the zero suppression (ZS) and selective readout (SR) algorihtms.
Output data format
Builds DCC event in DAQ format, including crystal data, trigger data and SR flags.
Data transmission
Data transmission to the central CMS DAQ with an average throughput of 200 MByte/s.
Spying and monitoring events are avaible for local DAQ.
Buffer occupancy monitoring and Trigger Throtling System interface
Error flags and statistics

6. DCC Technology VME 9U Format, VME64x complient, A32/D32 9 VirtexIIpro
70 optical inputs (68 FE+ 2 MEM channels)
1 SRP optical input
4 TCC electrical LVDS links
TTCRx and 1 TTS interface
1 S-Link64 port
Spy Memory Block (16 MByte)
Output Data Bandwidth up to 528 MByte/s

7. DCC Block Diagram … … … Receiver Block #1 Input Handler #1 & #2
EVENT
BUILDER
1to24
EVENT
BUILDER
25to48
EVENT
BUILDER
49to70
SR LINK
Receiver Block #1
Input Handler #1 & #2
TTS LINK
DAQ oFIFO
BOARD
CONTROL …
VME INTERFACE
List of Events in oFIFO
1to24
Receiver Block #1
Input Handler #23 & #24
TTC RX
REFCLK
FANOUT
List of L1A waiting
DAQ oFIFO
OPTICAL RECEIVERS …
List of Events in oFIFO
25to48
528 MB/s
64b - 66MHz
SLINK 64
Central
DAQ
DAQ oFIFO
Receiver Block #3
Input Handler #67 & #68
List of Events in oFIFO
49to68
OUTPUT
HANDLER
TCC LINK …
TCC LINK
TCC LINK
Receiver Block 3
Input Handler #69 & #70
(monitoring)
DAQ oFIFO
TCC LINK
SPY oFIFO
Local Bus
(VME)
List of Events in oFIFO
69to70

8. DCC-TC System DCC-TC DCC
TTCVi
DCC TC Main Functions
Emulation of the sub-system interfaces (FE,TCC and SRP)
to the DCC
Storage of simultated data
(~1000 complete events)
Control of the TTCvi
LOGIC
Altera
24 Optical
Links
Trigger
Orbit
Memory
Optical Module
24 Optical
Links
Optical Module
VME
Interface
Logic
24 Optical
Links
Optical Module
SR Flags
Transmitter
1 Optical Link
4 LVDS electrical
Links
TCC Event
Transmitter

9. Frame Length, M, Tower/SXtal ID
FE Interface
FE Data Block
( 284 x 16 bits, for 10 samples )
Event Memories
6 SRAM [ 8Mbit]
12x16 bits
#1 to #8
12 GOL Chips
Optical
Drivers
3x8
channels
DATA BUS (16 bits)
BX ID
ADDRESS BUS (18 bits)
#9 to #16
EV ID
CONTROL
Frame Length, M, Tower/SXtal ID
DATA BUS (16 bits)
Strip ID
#17 to #24
Xtal ID
Event Memories
6 SRAM [8 Mbit]
12x16 bits
12 GOL Chips
ADC Sample …
Trailer
The Optical Module (OM) mezannine board, emulate the FE interfaces to the DCC.
Each FE Board is responsible for the readout of crystal data from a TT (EB) or from a super crystal (EE).
Simulated crystal data are stored in the OM memories (4MBit/channel).
GOLs transmit high speed data (800 MBit/s) using an optical link with G-link or Gbit-Ethernet protocols.
3 OM ensure the 68 FE and the 2 MEM links to the DCC.

10. TCC Interface
TCC Data Block ( 72 x 16 bits)
TCC Transmitter
LVDS Serializer
BX ID
TCC
Memory
EV ID
LVDS Serializer
TCC ID
TPG #1
LVDS Serializer
TPG #2 …
DATA BUS (16 bits)
LVDS Serializer
TPG #68
ADDRESS BUS (18 bits)
Trailer
CONTROL
The TCC Transmitter emulates the TCC interface to the DCC.
Each TCC receives trigger data (EB) and pseudo-strip energy sums (EE) from the FE boards. After synchronization (and final calculation of the trigger primitives in the EE), trigger data are transmitted to the Regional Trigger and after a L1A to the DCC.
Simulated trigger data are stored in the TCC memory (8 MBit).
Data are transmitted to the DCC through 1 (EB) up to 4 (EE) LVDS electrical links.

11. SRP Interface
SR Flags Transmitter
SR Data Block ( 21 x 16 bits)
BX ID
EV ID
SR Flags
Memory
16bits
GOL Chip
Optical Driver
SRP ID
SRF #4
SRF #3
SRF #2
SRF #1 …
DATA BUS (16 bits)
ADDRESS BUS (18 bits)
SRF #68
SRF #67
SRF #66
SRF #65
CONTROL
Trailer
The SR Flags Transmitter emulates the SRP interface to the DCC.
The SRP is responsible for the determination of the SR flags, which depends on the transversal TT energy and its proximity to regions of high energy. After a L1A, SR flags are transmitted to the DCC.
Simulated SR Flags are stored in the SR Flag Memory ( 8 MBit).
SR Flags are transmitted through a single GOL Chip.

12. TTC Control and Trigger Generation
Controller
Trigger
Orbit
Memory
Trigger
Dispatcher
Trigger
FIFO
FE Data Manager A
FE Data Manager B
Orbit, L1A
TTCvi
FE Data Manager C
B-GO
SR Flags Manager
B-Go
generator
LHC Clock
TCC Data Manager
TTC Control
The DCC-TC controls the TTCvi by generating the LHC clock, the orbit signal, the L1A and the fast broadcast commands ( bx reset, event counter reset, reSync, and monitoring commands).
Trigger Generation
Trigger positions (bx and orbit positions) are stored in the trigger-orbits memory (8 Mbit). Physic triggers are generated by issuing a L1A for each trigger position.
Different latencies can be specified between the L1A and the different data transmitters.
Monitoring Triggers are identified through the TTC commands prior to the L1A transmission and are generated with a programmable orbit rate and bx position.

13. DCC-TC

14. DCC Configuration
DCC Configuration requires more than parameters:
Active Channels
DCC TTC codes
Operation Attributes
Data timeouts
ZS levels
Spying prescaling , …
Operation Modes
Forced readout ( ZS or Full Readout)
or Selective Readout, …
Cxtals Weights for ZS
6 weights and 1 factor for each cxtal

15. Data Model and Raw Data Simulation
Signal input: jets 50<pt<100 GeV at high luminosity (L~1034/cm2/s ).
Full ECAL detector simulation with ORCA.
ECAL raw data was simulated with an additional developed package and made persistent as ASCII files.
Data Simulation Handling
Data files are parsed and software objects representing the DCC input data blocks instantiated.
Different trigger conditions can be tested with the same data through a trigger generator.
Data are loaded in the DCC-TC memories and the expected DCC events are emultated based on the readout configuration of the DCC.

16. ECAL Crate controller & SOAP messages for commands,
DCC Test Bench
ECAL CRATE
Access ORACLE DB
for configuration
ECAL Crate Software
SBS
XDAQ
Crate
software
DCC
DCC TESTER
XDAQDStore
Device
drivers
DCC GUI for Local Tests
S-Link
ECAL Crate controller &
Run Control GUIs
FEDkit
XDAQ
GIII
DCC Tester XDAQAp.
DCC Tester GUI
SOAP messages for commands,
i2o messages for data
XDAQ
Device
driver

17. Conclusions
A prototype of the CMS ECAL Data Concentrator with full functionality was built and is under test.
A dedicated test system including a DCC Tester board emulating all DCC interfaces was developed.
The test system allows to validate the DCC hardware with simulated physics events at the highest L1 trigger rate.