1. Pingli Huang and Yun Chiu
A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs
Pingli Huang and Yun Chiu
Illinois Center for
Wireless Systems
Introduction
Calibration Algorithm (I)
Modern wireless communication systems demand low-power pipeline ADCs
Bluetooth, IEEE a/b/g, DVB-T, and etc.
SHA-less pipeline ADC can be used in IF sampling applications for DVB-T systems
Pipeline ADC architectural power efficiency
SHA-less multi-bit-per-stage architecture is the most power efficient
Severe performance degradation at high input frequencies due to sampling clock skew
Without sampling clock skew, residues are bounded between ±Vref/2
With sampling clock skew, some residues are pushed exceeding ±Vref/2
Sampling clock skew in SHA-less Architecture
Effectively creates dynamic offsets in the sub-ADC
Problem exacerbates with large input slew rates
Proposed approach
Calibrate sampling clock skew
Improve the viability of SHA-less multi-bit-per-stage architecture at high input frequencies
ADC Conversion errors occur when residues exceed ±Vref
The larger the sampling clock skew, the more residues exceed ±Vref/2
Calibration Algorithm (II)
Calibration implementation
Two sub-ADC sampling timings are initially apart, with S/H sampling timing in between.
About 1800 gates, 8-bit digital delay control, 2000-Sample/update
The sub-ADC timing resulting in more out-of-bound residues is stepped towards the other
In steady state, both sub-ADC timings converge to the S/H sampling timing.
Simulation Results
Convergence of the algorithm
Conversion error free in tracking
Simulation Setup
Simulator
SIMULINK
Simulated architecture
2.5-b/s with calibration
Sine-wave Input signal
Full range 500 MHz
Comparator offset (σ)
15 mV
Comparator noise (σ)
5 mV
Clock skew among comparators (σ)
5 ps
LSB size of the digital delay line
4 ps
No. of samples observed per update
1000
1: error
0: correct