1. Chapter 8: Main Memory CSS503 Systems Programming
Prof. Munehiro Fukuda
Computing & Software Systems University of Washington Bothell
CSS503
Chapter 8: Main Memory

2. Loading and Swapping New code is loaded into a process memory space.
An IO-blocked process (P2) is swapped out to the swap area.
A process ready to use I/O (P3) is swapped in the memory.
Use the Unix top command to see which processes are swapped out.
Operating
System
Process P1
File System
Loader: execlp( ), dlopen( )
/home/user/a.out
Process P2
Page-out
Paging Space
Process P2
Process P3
Page-in
Process P3
CSS503
Chapter 8: Main Memory

3. Logical versus Physical Address
Logical Address
Is independently allocated to each process.
Always starts with a given address for main( ).
Generated and used by a program.
Referred to as virtual address.
Physical Address
Is the set of all DRAM memory space.
Is address seen by the memory unit.
May includes part of multiple logical address spaces.
00…000
Process 1
Kernel
00…000
Kernel
PCB
Code
main( )
PCB
Process 2
Stack
00…000
Heap
Kernel
Code
main( )
Stack
Stack
Heap
Heap
PCB
FF…FFF
Code
main( )
Code
main( )
Stack
Heap
FF…FFF
PCB
Memory Management Unit
FF…FFF
CSS503
Chapter 8: Main Memory 2

4. Memory Management Unit
Physical address: The actual hardware memory address.
32-bit CPU’s physical address 0 ~ ( – FFFFFFFF)
1GB’s memory address 0 ~ ( – 4FFFFFFF)
Logical address: Each program assumes the starting location is always 0 and the memory space is much larger than actual memory
Operating
System
000000
Process P1
MMU
base
Logical
address
Physical
address
300040
300040
Process P2
CPU
300386
346
420940
120900
limit
Process P3
CSS503
Chapter 8: Main Memory

5. Memory Allocation Strategies
Key Idea
Pros
Cons
Contiguous
Allocate a logical space to a contiguous space of physical memory
Semantically easy
No memory fault
External fragmentation
No shared memory
Paging
Divide a logical space into pages and allocate them to physical space
No more external fragmentation
Shared pages available
Internal fragmentation
Page faults
Two memory accesses
No more semantically contiguous space
Segmentation
Give multiple contiguous logical spaces to each process
External fragmentation if mapped like contiguous strategy
Modern Architecture: Segmentation with Paging in TLB (Translation Look-aside Buffer) Support
CSS503
Chapter 8: Main Memory

6. Contiguous Memory Allocation
Operating
System
000000
For each process
Logical space is mapped to a contiguous portion of physical space
A relocation and a limit register are prepared
Process P1
MMU
relocation
register
Logical
address
Physical
address
300040
300040
Process P2
CPU
yes
300386
346
<
420940
120900
limit register
Process P3
CSS503
Chapter 8: Main Memory

7. Fixed/Variable-Sized Partition
Fixed-Sized Partition
Variable-Sized Partition
Operating
System
Operating
System
Operating
System
Operating
System
Process P1
Process P5
Process P5
Process P5
Process P8
Process P9
Process P4
Process P2 ?
Process P3
Process P2
Process P2
Process P2
Each partition is allocated to a process
How about a bigger process?
Any size of processes, (up to the physical memory size) can be allocated.
First, best, or worst fit?
Holes (free spaces) still remain.
CSS503
Chapter 8: Main Memory

8. External Fragmentation
Problem
50-percent rule: total memory space exists to satisfy a request, but it is not contiguous.
Solution
Compaction: shuffle the memory contents to place all free memory together in one large block
Relocatable code
Expensive
Paging: Allow non-contiguous logical-to-phyiscal space mapping.
Operating
System
Process P1
Shift up?
Process P3
Process P2
Can’t fit
CSS503
Chapter 8: Main Memory

9. Paging Physical space is divided in 512B~8KB-page frames (power of 2).
The logical space is a correction of sparse page frames.
Each process maintains a page table that maps a logical page to a physical frame.
Frame
Number
Page 0 1
Page 1 1 4 1
Page 0 2 3
Page 2 2 3 7
Page
Table
Page 3 3
Page 2 4
Page 1
Logical
Memory 5 6 7
Page 3
Physical
Memory
CSS503
Chapter 8: Main Memory

10. Address Translation A process maintains its page table
CPU
Logical Address
A process maintains its page table
PTBR (Page Table Base Register) points to the table.
PTLR (Page Table Length Register) keeps its length.
Logical address consists of:
Page number (e.g., 20bit)
Page offset (e.g., 12bit)
Address translation:
If p > PTLR error!
frame = *(PTBR + P)
Physical = frame << 12 | d
page index
displacement f
PTBR
PTLR
frame f d
MMU
frame #
displacement
Physical Address
Physical Memory
(DRAM)
CSS503
Chapter 8: Main Memory

11. Paging Example Page size 4 bytes Logical memory 16 bytes 4 pages
Physical Memory
addr
value
00000
00001
Page size
4 bytes
Logical memory
16 bytes
4 pages
Physical memory
32 bytes
8 frames
Note:
In general logical memory is much larger than physical memory.
Pages not fitted to physical memory are paged out to disk.
00010
00011
00100 i
00101 j
Logical Memory
00110 k
addr
value
Page Table
00111 l
01000 m
0000 a
index
frame#
01001 n
0001 b 00
101
01010 o
0010 c 01
110
01011 p
0011 d 10
001
01100
0100 e 11
010
01101
0101 f
01110
0110 g
01111
0111 h
10000
1000 i
10001
1001 j
10010
1010 k
10011
1011 l
10100 a
1100 m
10101 b
1101 n
10110 c
1110 o
10111 d
1111 p
11000 e
11001 f
11010 g
11011 h
11100
CSS503
Chapter 8: Main Memory
11101
11110
11111

12. Internal Fragmentation
Process0
Page 0
Problem
Logical space is not always fit to a multiplication of pages. (In other words, the last page has an unused portion.)
Solution
Minimizing page size
Side effect: causes frequent page faults and TLB misses
Process0
Page 1
Process0
Page 0
Page 2
unused
Process1
Page 0
Full pages!
Process3
Logical space
Process1
Page 1
Process1
Page 0
Page 2
unused
Process2
Page 1
Process2
Page 0
Page 2
unused
CSS503
Chapter 8: Main Memory

13. Paging Hardware with TLB
MMU
Providing a fast-lookup hardware cache
TLB: Translation Look-aside Buffer
TLB Operations
Refer to TLB to see if it caches the corresponding frame number
Upon a TLB hit, generate a physical address instantly
Upon a TLB miss, go to an ordinary page table reference.
TBL Flush
Performed every process context switch
Two memory accesses!
DRAM Memory
CSS503
Chapter 8: Main Memory

14. Discussions 1
Discuss about the pros and cons of large and small page size.
How does TLB contribute to making thread context switch cheaper than process context switch?
Consider cases when TLB is not so useful.
CSS503
Chapter 8: Main Memory

15. Memory Protection Why valide/invalid?
Each page table entry has various flags:
Read only
Read/Write
Valid/invalid
Why valide/invalid?
All pages may not be loaded at once
Only necessary pages should be loaded
Unloaded pages’ entry must be invalid.
Page 0
Page 1 1
Page 2 2
Page 0
Frame#
Valid/Invalid bit
Page 3 2 v 3
Page 1 1 3 v
Page 4 4
Page 2 2 4 v
Page 5 5 3 7 v 4 8 v 6 5 9 v 7
Page 3 6 i 8
Page 4 7 i 9
Page 5 :
Page n
CSS503
Chapter 8: Main Memory

16. Shared Pages Shared code
Read-only (reentrant) code shared among processes
Shared code appeared in same location in the physical address space
Private code and data
Each process keeps a separate copy of the code and data, (e.g., stack).
Private page can appear anywhere in the physical address space.
Copy on write
Pages may be initially shared upon a fork
They will be duplicated upon a write
vi 1 3
vi 2 4 1
data 1 6
vi 3 2
data 3 1
data 1 3
vi 1
page
table
vi 1 3 4
vi 2
Process 1
vi 2 6 5 6
vi 3 7 6
vi 3
data 2
page
table 7
data 2
vi 1 3
Process 2 8
vi 2 4 9 6
vi 3 10 2
data 3
page
table
Process 3
CSS503
Chapter 8: Main Memory

17. Two-Level Page-Table Scheme
A logical address (on 32-bit machine with 4K page size) is divided into:
a page number consisting of 20 bits.
a page offset consisting of 12 bits.
If each page entry requires 4 bytes, the page table itself is 4M bytes!
Two-level page-table scheme
Place another outer-page table and let it page the inner page table
the page number is further divided into:
a 10-bit page number. (1K entries)
a 10-bit page offset. (1K entries)
Thus, a logical address is as follows:
page number
page offset p1 p2 d 10 12
P1: outer page index
P2: page index
D: offset in a page
CSS503
Chapter 8: Main Memory

18. Two-Level Page-Table Scheme Example
Address-translation scheme for a two-level 32-bit paging architecture
Outer-page table with 1K entries: size = at least 4K
Inner page table with 1K entries: size = at least 4K
If a process needs only 1K page outer/inter page tables require only 8K, and thus the total process size = 9K.
More multi-level paging:
Linux (three levels: level global, middle, and page tables)
Windows (two levels: page directory and page tables) etc.
page number
page offset p1 p2 d 10 12 p1 p2
outer page table d
inner page table
CSS503
Chapter 8: Main Memory
destination page

19. Segmentation Each page is only a piece of memory but has no meaning.
Data
Code
Stack
Heap
user view of memory
Each page is only a piece of memory but has no meaning.
A program is a collection of segments such as:
main program,
procedure,
function,
global variables,
common block,
stack,
symbol table
Code
Data
Heap
Stack
logical memory space
CSS503
Chapter 8: Main Memory

20. Segmentation Architecture
STBR(Segment Table Base Register) S
limit
base
STLR(Segment Table Length Register)
Segment top address
CPU
offset
< + S D
Segment length no
Logical address = <segment#, offset>
trap: segmentation error
Very resemble to a contiguous memory allocation, while a process consists of several meaningful segments
CSS503
Chapter 8: Main Memory

21. Segmentation Example offset d2 offset d1 SP d1 used Currently executedPC d2
Stack top
used
CSS503
Chapter 8: Main Memory

22. Segment Protection and Sharing
Segment protection can be achieved by implementing various flags in each segment table entry:
Read only
Read/Write
Unlike a page, a segment has an entire code.
Thus, sharing code is achieved by having each process’ code segment mapped to the same physical space.
CSS503
Chapter 8: Main Memory

23. Segmentation with Paging
Is very resemble to a contiguous memory allocation
Causes External fragmentation
Introducing the idea of paging
Assuming
The segment size is 4G bytes, and thus the segment offset is 32 bits
a page is 4K bytes, and thus the page offset requires 12 bits.
Logical address = <segment#(13bits), segment_offset(32 bits)>
If segment# > STLR, cause a trap.
If offset > [STBR + segment#]’s limit, cause a segmentation fault.
Liner address = <[STBR + segment#]’s base | segment_offset>
Decompose liner address into <p1(10 bits), p2(10 bits), page_offset(12 bits)>
The first 10 bits are used in the outer page table to page the inner page table
The second 10 bits are used in the inner page table to page the final page
Physical address = <[PTBR + p2]’s frame# << 12 | page_offset>
CSS503
Chapter 8: Main Memory

24. Segmentation with Paging – Intel Pentium
13bits
1bit
2bits
32bits (4GB segment space)
GDTR
LDTR
selector#
Tbl indicator
Rqstr Priv.
offset
0: GDT
1: LDT
segment descriptor
limit
base +
Segmentation Phase
CPU
segment tables
10bits
10bits
12bits (4KB page space)
directory
table
offset
CR3
page directory
Table register
directory entry
Paging Phase
page table entry
page directory
DRAM
page table
Physical address
CSS503
Chapter 8: Main Memory

25. Linear Address in Linux
Linux uses only 6 segments (kernel code, kernel data, user code, user data, task-state segment (TSS), default LDT segment)
Linux only uses two of four possible modes – kernel and user
Uses a three-level paging strategy that works well for 32-bit and 64-bit systems
Linear address broken into four parts:
But the Pentium only supports 2-level paging?!
global directory
middle directory
page directory
offset
0 bit
CR3
bypassing
global dir entry
middle dir entry
page table entry
physical addr
CSS503
Chapter 8: Main Memory 24

26. Discussion 2 Discuss about the textbook exercises: 8.8 8.12 8.19 8.23
8.25
8.28
CSS503
Chapter 8: Main Memory