1. Breakout Session: Controls
Timing and Event System
S. Allison, M. Browne, B. Dalesio, J. Dusatko, R. Fuller, A. Gromme, D. Kotturi, P. Krejcik, S. Norum, D. Rogind, H. Shoaee, M. Zelazny

2. Outline Overview and HW Block Diagram
Performance of timing system for injector commissioning
Outstanding Issues
Task List
BC2 installation Status & Long-Haul Fiber Issues

3. Timing and Event Architecture
New LCLS Timing System ~
Linac main drive line
Low Level RF
FIDO
Beam Synchronous Acquisition
119 MHz
360 Hz
SLC
MPG P N E T I O C E V G F A N
SLC
events
LCLS
events
fiber
distribution
Precision<10 ps *
EPICS Network
Digitizer
LLRF
BPMs
Toroids
Cameras
GADCs
SLC klystrons I O C E V R D E V
TTL * m P P N E T S T B
TTL-NIM
convert.
*MicroResearch
SLC Trigs

4. Hardware Block Diagram 2007 Commissioning
Modulator
Triggers
Existing
Control
System
Beam Path
Acq and
Calibration
Triggers
BPM FEE
PADs and PACs
Timing
Crate
Acc and
Standby
Triggers E V G F A N 1 F A N 2 P N E T I O C
E V R I O C
E V R 1
E V R 2
E V R 3 I O C
360Hz
Fiducial RF
Timing
BPM
Crates
LLRF
Crate
119MHz
Clock
Future
MPS
Beam Rate,
Beam Path
Fiber Distribution:
Timing Pattern, Timestamp, Event Codes
TORO FEE
Triggers
Triggers
Trigger F A N 3
E V R 1 C A M 1 I O C 1
...
E V R 8 C A M 8 I O C 8
E V R 1 C A M 1 C A M 2 I O C 1 …
E V R 4 C A M 7 C A M 8 I O C 4
Laser
Steering
Crate F A N 4
E V R I O C
Profile
Monitor
Crate
Toro
Farc
Crate … …

5. Progress since Oct, 2006
Installation in sector 20 and 21 commissioned !
Successfully integrated it with the SLC Timing System
Finished hardware bench testing
Finished PMC-EVR driver
EVG sequence RAM programming at 360Hz, conditional logic is fairly basic, but does the job.
Event pattern records and timestamp distribution on the EVR IOCs
Finished cabling plans and documentation
Finished beam-synchronous acquisition

6. Diagram shows IN20 / LI20 Event System installation
IN20 Installation
Diagram shows IN20 / LI20 Event System installation
Top-Level shows connections to SLC Timing, MDL
The EVG Crate is shown with its fanouts to all subsystems

7. Tallies for 2007 Commissioning
# EVRs = 31 (mostly PMC)
# IOCs with EVRs = 28
# EVR Fanouts = 4
# Hardware Triggers = 120 and counting
All TTL except 2 NIM triggers for QDCs
Most require short cables (except LLRF)
EVR with clock now available for BC2 installation
All acquisition electronics using either internal clocks, clock output from the RF timing system, or other external clocks

8. Event System Functionality
Event Generator IOC:
Send out proper event codes at 360Hz based on:
PNET pattern input (beam code and bits that define beam path and other conditions)
Add LCLS conditions such as BPM calibration on off-beam pulses , diagnostic pulse etc.
Future – event codes also based on new MPS and user input
Send out system timestamp with encoded pulse ID from PNET
Send out PNET pattern to be used by SLC-aware IOCs
Manage user-defined beam-synchronous acquisition measurement definitions (event definition or EDEF)
Check for match between user EDEFs and input PNET pattern at 360Hz and tag matches in outgoing pattern

9. Event System Functionality, cont
Event Receiver IOC:
Set trigger delays, pulse widths, and enable/disable via user requests (not yet done on a pulse-by-pulse basis)
Set event code per trigger (triggering done in HW when event code received)
Receive event pattern 8.3 msec before corresponding pulse
Perform beam-synchronous acquisition based on tags set by EVG in the event pattern
Perform beam-synchronous acquisition for the SLC-aware IOC based on the PNET part of the event pattern
Process pre-defined records when specific event codes are received (not yet available – bug!)

10. EVG Event Time Line – 4 Fiducials
360Hz Fiducial
F0 (n=0)
F1 (n=1)
F2 (n=2)
F3 (n=3)
Time (msec)
1.0
2.8
5.6
8.3
9.3
HW starts sending event codes, starting with fiducial event code R0 R1 R2 R3
Receive Fn+3 PNET, determine Fn+3 LCLS pattern, and advance pipeline (n-2->n-1->n) P0 P1 P2 P3 L0 L1 L2 L3
Send LCLS pattern
Set Event Codes in Alt RAM based on the last patterns for Fn+1 E1 E2 E3 E4
120Hz BEAM
B-3 B0

11. Trigger Event Time Line – 1 Beam Pulse (B0)
Record processing (event, interrupt)
Hardware Triggers
Receive pattern for 3 pulses ahead
Triggering Event Codes Start
Beam
Kly Standby
Event Timestamp, pattern records, and BSA ready
Acq Trigger
Kly Accel
Fiducial Event Received
Fiducial F3 B0 18
500
1023
Time (usec)
0.3
100

12. Trigger Control Display

13. Trigger Event Assignment Display

14. EVG Displays

15. The Event System HW is performing as expected
Issues
The Event System HW is performing as expected
At the first order - still in its infancy
Outstanding problem (presumably software) where CPU hangs when EVR interrupts are enabled. Some IOCs running without interrupts (hardware triggers but without timestamps, BSA, or event code IRQs).
Documentation and help screens still to be done.
EVG IOC doesn’t know when there’s no beam, only when beam is possible – limits trigger conditions.
Software not yet in place to handle hardware and communication errors.

16. LCLS Event System for Beam Synchronous Data Acquisition
All pulsed readback devices
BPMs
Cameras
RF phase and amplitude
Bunch length monitors
Loss monitors
Can be read simultaneously on a single pulse, throughout the machine
With a repetition rate of 120 Hz

17. Beam Synchronous Acquisition (BSA)
EVG Event Definitions (EDEFs) are used for BSA
EDEF includes:
Beam code
SLC PNET bits and LCLS Modifier bits
No. of pulses to average, no. of pulses to measure
Client or System name
Permanent System EDEFs that are always active:
1Hz, 10Hz, Full, Single Shot, Feedback
Available to all clients
Client applications may reserve a Client EDEF
Client receives EDEF # assignment on demand
Client proceeds to fill out definition, then sets “GO”

18. Slots for 20 possible Event Definitions allocated
User
Defs
Fixed
Defs

19. User interface for defining an Event Def

20. Example of Data Fanout 20 Buffers One for each EDEF
2800 samples per buffer

21. Current Activities
Software - fix hang problem, add HW error detection and recovery
Next installation phase is BC2 (sectors 21 to 30):
60 EVRs to be ordered - 34 VME, 26 PMC – critical path
5 fanout modules (1 every 2 sectors)
SW - only DB and display work planned
Long Haul Fiber Test
Integrate new LCLS MPS and Master Pattern Generator (MPG):
Make EVG aware of MPS trips
Rate-liming logic including beam “burst” and “single-shot” modes
Send out PNET pattern to EVG and CAMAC controls (for modulator triggers)
Beyond BC2:
BSY/LTU/Undulator Procurement and Plans
Changes to EVR firmware to change behavior when multiple triggers on a single pulse
Generic trigger delay scan package
Bunch charge change on pulse-by-pulse basis?
More complex conditional logic for event codes (EVG) and pulse-to-pulse changes in trigger attributes?

22. Challenges in extending the LCLS timing system beyond the injector
biggest challenge is Long-Haul distribution of timing data via the Fiber-Optical (F-O) Links
Reasons
MRF Event System is designed around Multi-Mode SFP (Small Form-Factor Pluggable) F-O links which allow a maximum fiber length of ~300 meters
Our requirements include runs of several Kilometers (at least)
Cannot daisy-chain the event F-O links: exceeds the jitter budget
Temperature effects on long fibers – drift, but how bad?

23. Long-Haul Fiber Distribution
Proposed Solution: New HW and some testing
Single-Mode, pin-compatible SFP modules are commercially available (Agilent ACFT-57R5)
Allows us to go ~10KM
Plugs into our event system HW
Does not solve temperature-induced phase-drift problem
Solve this by:
Running Long Fiber in temperature-controlled environment
Re-Syncing EVRs to a locally-distributed 119MHz source
Long-haul fiber test:
Function of Single-Mode SFP Modules
Drift, Trigger time jitter, Phase Noise

24. Long-Haul Event Fiber System Test
What it will determine:
Function of Single-Mode SFP Modules
Drift, Trigger time jitter, Phase Noise
Compare two EVR’s triggers & RF Clocks
One EVR Short-Haul
Other EVR Long-Haul
Also compare to reference RF Clock