1. An Efficient Approach for Designing and Minimizing Reversible Programmable Logic Arrays
Sajib Kumar Mitra, Lafifa Jamal
and Hafiz Md. Hasan Babu*
Department of Computer Science and Engineering
University of Dhaka, Dhaka-1000, Bangladesh s:
Mineo Kaneko
School of Information Science Japan Advanced Institute of Sci. and Tech. s:

2. Purposes Define an new Architecture of RPLAs
Minimization of Quantum Cost
Reduction of Critical Path Delay
Reduction of Number of Gates
Garbage Outputs Optimization

3. Overview Reversible and Quantum Computing
Quantum Realization of Reversible Circuits
Reversible Programmable Logic Arrays
Proposed Architecture of Reversible PLAs
Delay Calculation of Reversible PLAs
Performance Analysis
Conclusion

4. Reversible and Quantum Computing

5. Reversible Computing Equal number of input states and output states
Preserves an unique mapping between input and output vectors for any Reversible circuit
One or more operations can be united called Reversible Gate
(N x N) Reversible Gate has N number of inputs and N number of outputs where N= {1, 2, 3, …}
[1] A. K. Biswas, M. M. Hasan, A. R. Chowdhury, and H. M. H. Babu, “Efficient approaches for designing reversible binary coded decimalimplement in a single adders,” Microelectronics Jounrnal, vol. 39, no. 12, pp. 1693–1703, December 2008.

6. Reversible Computing…
Fig. 1: Basic difference between Irreversible and Reversible Circuits
Limitation
Feedback is strictly restricted
Fan-out must be one always

7. Reversible Computing…
Fig. 2: Popular Reversible gates

8. Quantum Computing
In Quantum Computing, encode information as a series of quantum-mechanical states such as spin directions of electrons or polarization orientations of a photon that might represent as or might represent a superposition of the two values.
Encoded data is represented by qubits rather than bits which can perform certain calculations exponentially faster than conventional computing.
[2]W. N. N. Hung, X. Song, G. Yang, J. Yang, and M. Perkowski, “Quantum logic synthesis by symbolic reachability analysis,” in 41st Conference on (DAC’04), Design Automation Conference, May 2004, pp. 838–841.

9. Fig. 3: Reversible behavior of Quantum matrix operation
Quantum Computing…
Quantum Computation uses matrix multiplication rather than conventional Boolean operations and the information measurement is realized by calculation the state of qubits .
The matrix operations over qubits are simply specifies by using quantum primitives. For example,
Fig. 3: Reversible behavior of Quantum matrix operation

10. Fig. 4: Working Principle of Unitary Controlled NOT (UCN)
Quantum Computing…
Input
Output A B P Q 1
Input/output Pattern
Symbol 00 a 01 b 10 c 11 d
Fig. 4: Working Principle of Unitary Controlled NOT (UCN)

11. Quantum Realization of Reversible Circuits

12. Fig. 5: Several Quantum Primitives
Quantum Cost
Quantum Cost (QC): Total number of 2x2 quantum primitives (4x4 unitary matrices) which are used to form equivalent quantum circuit of any Reversible Circuit.
Fig. 5: Several Quantum Primitives
[3] M. Perkowski and et al, “A hierarchical approach to computer-aided design of quantum circuits,” in 6th International Symposium on Rep-resentations and Methodology of Future Computing Technology, 2003, pp. 201–209.

13. Orientation of Quantum Gates
The attachment of SRN (Hermitian Matrix of SRN) and EX-OR gate on the same line generates symmetric gate pattern has a cost of 1.
Here T= V or V+
Fig. 6: Difference interactions between Quantum Primitives

14. Quantum Cost of Reversible gates
Fig. 7: Equivalent Quantum Circuits of Reversible Gates

15. Working Principle of Quantum Circuit
How does Quantum circuit work?
Fig. 8: Toffoli Gate and corresponding Quantum Circuit

16. Working Principle of Quantum Circuit…
INPUT
OUTPUT A B R C 1 C’
Fig. 9: Working Principle of Quantum Equivalent of TG

17. Working Principle of Quantum Circuit…
INPUT
OUTPUT A B R C 1 C’
Quantum Cost of Toffoli Gate is 5

18. Working Principle of Quantum Circuit…
Alternate representation of Quantum circuit of TG…

19. Proposed Quantum Circuit of NFT
Fig. 9: Quantum Realization of NFT Gate (QC= 5)

20. Proposed Quantum Circuit of NFT…

21. Proposed Quantum Circuit of NFT…

22. Proposed Quantum Circuit of NFT…

23. Proposed Quantum Circuit of NFT…

24. Proposed Quantum Circuit of NFT…

25. Proposed Quantum Circuit of NFT…

26. Proposed Quantum Circuit of NFT…

27. Proposed Quantum Circuit of NFT
Fig. 9: Quantum Realization of NFT Gate (QC= 5)

28. Reversible Programmable Logic Arrays

29. Reversible Programmable Logic Arrays
Reversible Programmable Logic Arrays was first proposed by A. R. Chowdhury for multi-outputs function in [1] (Fig. 1).
Fig. 1: Existing design of Reversible PLAs.

30. Reversible Programmable Logic Arrays (cont…)
Limitation of Previous Design:
1. Toffoli gate produces huge number of unused outputs which are same as primary inputs.
2. Used Conventional Architecture (Complement and non-complement lines for copying input variables)
3. Generates huge number of Gates and garbage

31. Proposed Architecture of Reversible PLAs

32. Proposed Architecture of Reversible PLAs
Proposed Design of RPLAs composed of followings:
1. EX-OR plane Optimization by using FG
2. Construction of AND plane by using MUX and FG
3. Delay Calculation based on Greedy Approach
We have used the following example to represent the Proposed Design of RPLAs.

33. Proposed Architecture of Reversible PLAs (cont…)
Construction of EX-OR plane :
1. EX-OR plane is constructed based on the ordering of the size of Products of functions
2. EX-OR plane defines the particular order of all products which will be followed by AND plane

34. Proposed Architecture of Reversible PLAs (cont…)

35. Proposed Architecture of Reversible PLAs (cont…)
Construction of AND plane :
1. AND plane is constructed based on the ordering of the Products
2. MUX and FG gates are used to design AND plane
3. Two different patterns of MUX gates have been used in proposed design as follows:

36. Proposed Architecture of Reversible PLAs (cont…)

37. Proposed Architecture of Reversible PLAs (cont…)
Fig. 2: Proposed Architecture of Reversible PLAs.

38. Delay Calculation of Reversible PLAs

39. Delay Calculation of Reversible PLAs
We divide the calculation into two phases:
a. AND Plane Delay and
b. EX-OR Plane Delay
Then we have merged both of the delay respect to both planes. In further realization of delay calculation, we consider the following things:
a. Gate (Via) is represented as circle (DOT).
b. Delay of any gate is 1 and via (DOT) denotes 0.
c. Decimal value shows the delay of circle

40. Delay Calculation of Reversible PLAs (cont…)

41. Delay Calculation of Reversible PLAs (cont…)
Delay Calculation of AND Plane

42. Delay Calculation of Reversible PLAs (cont…)
Delay Calculation of EX-OR Plane

43. Performance Analysis

44. Performance Analysis

45. Conclusions
We have proposed a regular structure of Reversible Programmable Logic Arrays (RPLAs) based on MUX Feynman logic. We used the garbage outputs as operational outputs that reduced the number of AND operations in RPLAs. The minimization of AND plane based on the ordering of input variables gives an excellent throughput of the overall design. Finally, we figured the performance of the proposed design over the existing one. The experimental results show that the proposed design outperforms the existing one in terms of numbers of gates, garbages and quantum costs. The proposed algorithm also required less time than the existing one. We also presented five lower bounds on the numbers of gates, garbages and quantum cost of RPLAs.

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