1. Chapter 14 Arithmetic Circuits (II): Multiplier Rev. 1.0 05/12/2003
EE141
Chapter 14
Arithmetic Circuits (II):
Multiplier
Rev /12/2003
Rev /05/2003
Rev /12/2003

2. Binary Multiplication

3. Binary Multiplication

4. Array Multiplier

5. MxN Array Multiplier — Critical Path

6. Wallace-Tree Multiplier

7. Wallace-Tree Multiplier

8. Multipliers —Summary Identify Critical Paths
Possible techniques for speed up:
Multiplier Encoding (Booth encoding)
Wallace Tree Multiplier
Pipelining (multi-phase multiplication)

9. Shifters

10. The Binary Shifter

11. The Barrel Shifter
Area Dominated by Wiring

12. 4x4 barrel shifter
Widthbarrel ~ 2 pm M

13. Logarithmic Shifter

14. 0-7 bit Logarithmic Shifter3 2 1
Out3
Out2
Out1
Out0

15. Summary
Datapath designs are fundamentals for high-speed DSP, Multimedia, Communication digital VLSI designs.
Most adders, multipliers, division circuits are now available in Synopsys Designware under different area/speed constraint.
For details, check “Advanced VLSI” notes, or “Computer Arithmetic” textbooks