1. ECE 352 Digital System Fundamentals
Registers With Shared Logic
In this presentation, we will look at how registers with shared logic can be constructed and how they operate.

2. Variation on Design Method
So far, registers have had dedicated logic
Each register has its own logic to process input operands for its operations, including multiplexing to choose between values for different operations.
However, in some cases it is a good idea to be able to share this logic
Maybe there are many registers…
Maybe don’t need to do all register operations simultaneously…
Maybe the logic is quite large…
Processors often share logic among registers, since there are many more registers than the number of operations being performed
Most of the register design examples we’ve seen so far have utilized dedicated logic. Each register was self-contained with all the logic required to perform its operations. There are times when having dedicated logic may not be the best idea, though. For example, we may have many registers, but don’t need to perform an operation on all registers simultaneously. Or, the logic to perform the operation may be very large, so we don’t want to duplicate it in every register. These are the reasons that most processors use shared logic, since they have many registers but only perform one or a few operations simultaneously.

3. Shared Logic Example Three storage registers (R, T, U)
One data input (G)
Several control signals
Mux selects muxA, muxB, and muxS
Register load enables LDR, LDT, and LDU
What can this structure do?
Here’s an example circuit where multiple registers share a single adder circuit. The three registers, R, T, and U are basic storage registers. They can only hold their value or load a new one. The circuit has a single data input G. There are a total of six control inputs that determine what the circuit does. Three of them control the multiplexers and the rest each enable one of the registers. This circuit isn’t as flexible as one where each register can perform an addition. There is only a single adder, so only one addition can be performed per cycle. But what can this circuit do?

4. Shared Logic Example
Trace from register inputs to find their sources
Look at choices made by each multiplexer
Load input G or the result of R+T, R+U, T+T, or T+U into any of the three registers
Can load the same value into multiple registers simultaneously
Can NOT load different values into multiple registers simultaneously
To figure out what possible operations the circuit can perform, we trace backwards from each register’s data input to see what we can load into it. We find that any of the registers can be loaded with either the value of the input G, or one of four sums that can be generated by the adder. Note that the hardware cannot generate the sums R+R or U+U. Since all three registers can be loaded simultaneously and independently, we can store the output of mux S into any or all of them. However, it is not possible store a DIFFERENT value into multiple registers simultaneously—the input to every register comes from the same place.

5. Input Multiplexing Multiplexers may be used in several places…
To choose values for the inputs to the shared logic
To choose a source for a destination register
If the logic is shared, the first category of multiplexers is also shared…
Even with shared logic, there may be additional multiplexing at the register input
Allows multiple registers to simultaneously load different values
Selects between the result from the shared logic, external input(s), constant values, or even a result from some logic within the register
The flexibility of a circuit is dependent on the number and placement of multiplexers within the circuit. Multiplexers at the inputs of the shared logic choose the source(s) for each operation. We can also place multiplexers at the register data inputs to choose the source for each register. If we are sharing logic amongst registers, then we share that logic’s input multiplexers as well. Even when we are using shared logic, we may choose to add additional multiplexing at the register inputs so we can simultaneously load registers with results from different operations or values from other sources.

6. Shared Logic + Reg Input Muxes
Now, we can simultaneously update any register to either the adder result or input G
It is a trade-off between flexibility and circuit area!
Here’s our example circuit again, but now it has been modified so that each register input has its own independently-controlled mux. It still has the shared adder, but the circuit has become a little more flexible. We can now simultaneously update multiple registers and choose for each one whether it is updated with the adder output or the value on input G. Of course, this flexibility wasn’t free – we added two multiplexers to the circuit so it is larger and consumes more power. As we’ve seen repeatedly, design always involves making trade-offs.

7. Multiplexer-Based Transfers
A multiplexer at a register input can also support conditional transfers
Single destination has multiple possible sources, selected by some condition
Example:
if (K1=1) then (R0A)
else if (K2=1) then (R0B)
We can also use input multiplexers to perform conditional transfers, for the case where a single destination register has multiple sources that are selected based on some specified condition. In this example pseudocode describing the desired hardware behavior, we choose the value to load into the register based on the values of signals K1 and K2. In the corresponding circuit, we use a multiplexer to choose between A and B, and only enable the register when one of the listed conditions is true. Note that K1 has priority, since K2 is ignored when K1 is asserted. This behavior matches the pseudocode, because regardless of the value of K2, R0 will store A if K1 is 1.

8. “Generic” Register Diagram
Some logic and multiplexers are shared, but some are dedicated…
In general, we are not limited to registers with only shared logic or only dedicated logic. We can create a hybrid of the two, where some register operations are performed by shared logic and other register operations are performed by dedicated logic. In this case, register R0 has a dedicated mux that can select values coming from the shared logic or other registers, but it also can select results from its dedicated logic so it can perform certain operations entirely on its own.

9. Some Thoughts On Sharing
Sharing can save area because we “reuse” the same logic for multiple destination registers
But it limits what we can do in a single cycle…
If we have many registers that can be the destination for a given operation, this area can be significant
Dedicated muxes: many large muxes
Shared muxing: a few large muxes
The best choice depends on how the registers need to be used and the design constraints
There isn’t one choice that is right in all cases…
The choices involved in deciding whether to share logic are often complex. By sharing logic, we can reduce the circuit area, but it will limit the number and variety of operations that we can perform in a given clock cycle. When we have many registers that need to be able to store the results of a given operation, using a dedicated mux in each register will give the most flexibility at the expense of having many large muxes. The optimal choice for a given situation will depend balancing the need for flexibility with the allowable circuit area and all the other design constraints. There simply isn’t a single answer that’s always correct. The best solution will depend on the nature of the problem.

10. ECE 352 Digital System Fundamentals
Registers With Shared Logic
This concludes our video on registers with shared logic. We’ll put these ideas into practice in an upcoming video when we look at a datapath for a simple processor.