1. SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
6/12/2019
CE1901 Week 10, Class 1
FPGAs
The Cyclone II
The Cyclone IV (as described in our text)
The Cyclone V (as we use in lab)
Review Muddiest Point
SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
Dr. Josiah Yoder

2. Cyclone II Chip exterior
SE1011
6/12/2019
Cyclone II Chip exterior
SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
Dr. Josiah Yoder

3. Cyclone II Chip exterior
SE1011
6/12/2019
Cyclone II Chip exterior
SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
Dr. Josiah Yoder

4. Cyclone II – an FPGA (Field Programmable Gate Arrray)
SE1011
6/12/2019
Cyclone II – an FPGA (Field Programmable Gate Arrray)
Logic Elements (LE)
Input/Output Elements (IOE)
Dr. Josiah Yoder

5. SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
6/12/2019
Cyclone IV
SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
Dr. Josiah Yoder

6. SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
6/12/2019
Cyclone IV
Logic Elements (LE)
Input/Output Elements (IOE)
SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
Dr. Josiah Yoder

7. SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
6/12/2019
Cyclone V
SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
Dr. Josiah Yoder

8. SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
6/12/2019
Cyclone V
SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
Dr. Josiah Yoder

9. Cyclone V – A SoC (System on a Chip)
SE1011
6/12/2019
Cyclone V – A SoC (System on a Chip)
Input/Output Elements (IOE)
Logic Elements (LE)
CPU (ARM computer)
Dr. Josiah Yoder

10. SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
SE1011
6/12/2019
Muddiest Point
SE-1011 Slide design: Dr. Mark L. Hornick Instructor: Dr. Yoder
Dr. Josiah Yoder