1. Introduction to Computer Systems Engineering
Final Review
Introduction to Computer Systems Engineering
(CPEG 323)
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

2. Objectives of CPEG 323
Acquire solid knowledge in the analysis, design, implementation and evaluation of computer system organization with emphasis on instruction-set architecture and optimization
Acquire basic knowledge of the interaction between system software (e.g. compilers) and hardware (architecture) design
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

3. ABET Outcomes
Ability to apply knowledge of science (e.g., computer architecture and system organization, and related computer science issues), and engineering (e.g., performance analysis and benchmarking, ISA simulation and verification)
Ability to use the techniques, skills and modern engineering tools necessary for engineering practice
Knowledge of related topics in computer science discipline
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

4. Areas of Importance Basics of computer organization
Instruction set architectures
Computer arithmetic
Computer performance
Data path and control
Pipelining
Memory Hierarchy
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

5. Basics of Computer Organization
(Chapter 1 of text + slides Topic0, 1, 1a)
General knowledge of computing history
Historical perspectives
Impacts of technological changes
Market forces
How architecture is affected by software and applications
Basic structure of general purpose computer
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

6. Instruction Set Architectures
(Chapter 2 of book + Slides 2, 2a, 2b, 2c. 2d)
What is ISA ?
Role of ISA w.r.t. hardware and software
MIPS instruction set architecture
Basic Steps of MIPS instruction execution
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

7. More about ISA … 4 style of ISAs: General vs. special purpose regs
memory-to-memory
accumulator machines
stack machines
register based ISA
General vs. special purpose regs
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

8. More about ISA … MIPS memory model Register conventions
data types and sizes
little vs. big endings
Register conventions
MIPS operations (3 types)
instruction format and fields
addressing mode
assembly vs. machine representation
RISC vs. CISC
Calling conventions and stack frames
caller save vs. callee save
parameter passing
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

9. More about ISA … Static vs. dynamic libraries System software and ISA
role of system software tool chain: compiler, assembler, linker, etc.
memory layout for C compilers
runtime stack layout
Interaction between ISA and OS
Privileged mode, traps, etc
Static vs. dynamic libraries
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

10. Computer Arithmetic (Chapter 3 of book + Topics 3, 3a, 3b, 3c, 3d, 3e)
Number representations
un/signed integers
BCDs
Two’s complement
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

11. Computer Arithmetic – cont’d
Basic ALU design
Integer adders (ripple carry, look ahead techniques)
Integer multiply
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

12. Computer Arithmetic – cont’d
Real numbers
IEEE-754 Representation
FP Addition
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

13. Performance Evaluation
(Chapter 4 of book + Slides 4, 4a)
Why performance evaluation ?
Performance matrices
Performance measurement
Benchmarks
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

14. Performance matrices Time-based matrices CPI MIPS and MFLOPS
Hardware based matrics and weakness
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

15. Performance measurement and benchmarking
Sustained and peak performance
Relative performance
Benchmark classes
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

16. Processor Datapath and Control
(Chapter 5 of book + Slides 5, 5a, 5b)
Datapath building blocks
Single-cycle datapath and control
Multi-cycle datapath and control
And comparsion between them
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

17. Data Path and Control
Given an instruction, say, add or lw or sw, can you point out the correct setting of each control?
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

18. Data Path and Control 1-cycle implementation
Multi-cycle implementation
Finite-state machine Microcode
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

19. Pipelining Chapter 6, slides 6, 6a, 6b, 6c
Pipelined data path and control
Hazards
What are hazards
How many types of hazards?
Related concept: data dependence and its representation
Hazards resolution
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

20. A Pipelined Datapath 2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

21. Hazards Three types of hazards (data, control, structural)
Concept of data dependence and dependence graphs
Three types of data dependences that cause data hazards
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

22. Hazards Detection and Resolution
Hazards resolution
architecture vs. software methods
forwarding (bypassing)
stalls and interlock
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

23. Memory Hierarchy Chapter 7, slides 7, 7a, 7b, 7c, 7d, 7e
Memory hierarchy overview
Cache and cache design
Virtual memory
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

24. Memory Hierarchies
Q1: Where can a block be placed in the upper level? (Block placement)
Q2: How is a block found if it is in the upper level? (Block identification)
Q3: Which block should be replaced on a miss? (Block replacement)
Q4: What happens on a write? (Write strategy)
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

25. Cache Architecture The basics of cache Cache organization
Cache replacement policy
Cache design
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

26. Cache Basics What is cache ? Is it architecture visible ?
Locality: temporal and spacial
Cache hit/miss ratio
How to compute effective cache access time ?
Integration Cache in datapath design
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

27. Cache Organization Cache line and directory Cache organization
Fully associative: an element can be in any block
Direct mapping : an element can be in only one block
Set-associative : an element can be in a group of block
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

28. Memory Address TAG INDEX Offset within a block Block address
Example 1: the basic memory accesses unit is “word”, and one block has 4 words. Then this offset has 2 bits, pointing to a word in the block.
Example 2: the basic memory accesses unit is “byte”, and one block has 4 words, 1 word has 4 bytes. Then this offset has 4 bits, 2 bits pointing to a word in the block, another 2 bits to a byte in the word.
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

29. Cache Design
Cache parameters ( depending on organization and placement)
Cache replacement policy – LRU, OPT, etc.
Cache performance evaluation method
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

30. Virtual Memory Motivation of VM
Virtual to physical address mapping: page and page table
Page placement and size selection
Page fault and replacement policy
TLB: motivation and design issues
Protection
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt

31. VM vs. Cache Technology factors Hardware vs. software tradeoffs
2019/7/10
\course\cpeg323-05F\Final-Review F.ppt