1. Chapter 7 Microprogrammed Control
충남대학교 컴퓨터전공
이 철 훈

2. Fig. 7-1 Microprogrammed control organization
Chapter 7
Control Memory
Control unit : initiates sequences of µoperations
1. Hardwared control : control signals are generated by hardware using conventional logic design technique
- 속도가 빠르지만 수정이 거의 어렵다
2. Microprogrammed control : µoperations들이 control memory 상에 µprogram되어 있다.
- µinstruction fetch로 인해 속도가 느리지만 수정이 용이하다.
Fig Microprogrammed control organization
Computer System Architecture 1

3. Chapter 7
Address Sequencing
각 instruction들은 그 instruction을 수행하기 위한 µoperation 들을 발생시키기 위하여, control memory 상에 µprogram routine으로 구현
Address sequencing capabilities
1. Incrementing of the control address register
2. unconditional branch or conditional branch depending n status bit conditions
3. a mapping process from the bits of the instruction to an address for control memory
4. a facility for subroutine call and return
Computer System Architecture 1

4. Fig. 7-2 Selection of address for control memory
Chapter 7
Address Sequencing
Fig Selection of address for control memory
Computer System Architecture 1

5. Address Sequencing Conditional Branching Chapter 7
The status conditions are special bits in the system that provide parameter information such as the carry-out of an adder, the sign bit of a number, the mode bits of an instruction, and input or output status conditions
Conditional branch
∗ there are n status conditions in the system
∗ [ log2n ] bits in µinstruction are used to select one condition
∗ using multiplexer
Unconditional branch
∗ fixing the value of one status bit to 1
Computer System Architecture 1

6. Fig. 7-3 Mapping from instruction code to µinstruction address
Chapter 7
Address Sequencing
Mapping of Instruction
각 instruction을 구현한 control memory 상의 µprogram routine의 첫 번째 word로 branch 하는 것
이 경우 instruction의 opcode bit들이 status bit이 된다
An example
∗ opcode : 4 bits
∗ control memory : 128 words (→ 7-bit address)
∗ each instruction : up to 4 µinstructions
Fig Mapping from instruction code to µinstruction address
Computer System Architecture 1

7. Address Sequencing Subroutines Chapter 7 Common section of µcode
can be called from any point within the main body of µprogram
(ex) effective address computation
Must save and restore the return address
(ex) subroutine register (SBR)
Computer System Architecture 1

8. Microprogram Example Computer configuration Chapter 7
4 processor registers : AR, PC, AC, DR
2 control unit registers : CAR, SBR
Fig Computer hardware configuration
Fig Computer instructions
Computer System Architecture 1

9. Fig. 7-6 Microinstruction code format
Chapter 7
Microprogram Example
Microinstruction format
1. µoperation field (Tab. 7-1)
- 각 field로부터 µoperation을 하나씩 지정할 수 있으나, 이들은 서로 conflict가 생겨서는 안된다
- 그러나 ‘ ’은 010( AC ← 0)과 001( AC ← AC + DR )이 동시에 수행될 수가 없기 때문에 의미가 없다
Fig Microinstruction code format
Computer System Architecture 1

10. Microprogram Example Chapter 7 2. condition field (CD)
3. branch field (BR)
Computer System Architecture 1

11. Microprogram Example Symbolic microinstructions (5 fields) Chapter 7
1. label : symbolic address (colon (:)으로 끝남)
2. µoperations : upto 3 symbols (comma로 분리)
3. CD : one of the condition U, I, S, or Z
4. BR : one of the 4 branch symbols
5. AD : address field in one of 3 possible ways
(a) symbolic address 사용 (이것은 반드시 label에 명시되어야 함)
(b) N E X T symbol 사용 (next address in sequence)
(c) BR field가 MAP 이나 RET일 경우, AD field는 empty이다
Computer System Architecture 1

12. Microprogram Example The Fetch routine Chapter 7
µinstructions for the fetch routine
Symbolic µprogram for the fetch routine
Translated binary µprogram
Computer System Architecture 1

13. Fig. 7-2 Symbolic microprogram (partial)
Chapter 7
Microprogram Example
Symbolic µprogram
INDRCT subroutine
Fig Symbolic microprogram (partial)
Computer System Architecture 1

14. Fig. 7-3 Binary microprogram for control memory (partial)
Chapter 7
Microprogram Example
Binary microprogram
Fig Binary microprogram for control memory (partial)
Computer System Architecture 1

15. Fig. 7-7 Decoding of microoperation fields
Chapter 7
Design of Control Unit
Decoding of F fields
Fig Decoding of microoperation fields
Computer System Architecture 1

16. Design of Control Unit Microprogram sequencer Chapter 7
Fig. 7-8 Mircoprogram sequence for a control memory
Computer System Architecture 1
Tab. 7-4 Input logic truth table for microprogram sequencer