1. Computer Architecture
The CPU and the Fetch Decode Execute cycle
Animation

2. Memory
Data bus
Address bus
Registers PC
ACC
MAR
MDR
Control bus
CIR
Control
unit
ALU
Input / Output

4. The Fetch-Decode-execute cycle
The PC (program counter) has the address of the next instruction to fetch
The value in the PC (program counter) is copied into MAR (memory address register)
The CU (control unit) locates and fetches the data
If it is an instruction it is placed in the CIR (Current instruction register)
The PC is incremented by one
The instruction in the CIR is decoded by the control unit
Finally the instruction is is executed by placing any request for data into the MAR (memory address register) for the data to be collected and copied to the MDR
If it is data it is placed in the MDR (memory data register)