1. CS 140L Lecture 1
Professor CK Cheng
10/2/02

2. Behavior description
C, System C,
Verilog, VHDL
Register Transfer Level
Verilog, VHDL
Logic Synthesis
Netlist of Logic
Logic Diagram
Placement, Routing
Physical Layout
Mask Fabrication
FPGAs
Data representation
Progress, Design Automation
Analysis: Functional, Timing

3. FPGAs (Field Programmable Gate Arrays)
Programmable Logic Block
Switches
Switch Matrix
Wiring Channels
-SRAM based (Flash memory)
-antifuse
Disadvantages: Penalty on area, density, speed
Advantages: Flexibility, low startup costs, low risk, revisions without
changing the hardware

4. CMOS Logic (3.2 – 3.6)
Complementary Metal-Oxide Semiconductor

5. 1. Transistors (FET) Field Effect TransistorG
NMOS G W L D S S
G =1 => D =S {
D = 1 => S = 0.8
D = 0 => S = 0
G = 0 => D&S are separated.

6. D G L W r
c WxL , C D S C G
PMOS A B S
C ’
G = 1 => D&S are separated.
G = 0 => D =S {
D = 1 => S = 1
D = 0 => S = 0.2