1. Assignment
1) Explain how lower address bus is multiplexed with data bus? 2) Explain the function of all the control signals in the 8085 Control Logic Subsystem. 3) What is the use of stack pointer? Give two examples and explain both of them. 4) By using the architecture of 8085 explain fetch and execute of the following instructions. Refer pg STA 3020H - LDA 2000H - LDAX D - MOV A, M 5) Explain the status flags available in 8085 microprocessor.
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2. org 1000h lxi sp,3000h mvi a,10 lxi h,data1 add m cc mmm sta result jmp exit mmm: push psw sui 20h sta 2020h pop psw ret exit: end org 2000H data1: dfb FFh,22h,33h result: dfs 1
1) Translate the program into machine codes
manually.
2) Show the values of program counters
and the content of stack pointers during the
execution process of PUSH PSW & RET
3) How much time is required to execute the program
by using 3MHz crystal.
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3. 7/22/2019 ORG 1000H PC BYTE1 HEX BYTE2 BYTE3 Tstate1 Tstate2
LXI SP,3000H
1000 31 00 30 10
MVI A,10
1003 3E 0A 7
LXI H,DATA1
1005 21 20
ADD M
1008 86
CC MMM
1009 DC 12 9 18
STA RESULT
100C 32 03 13
JMP EXIT
100F C3 1A
MMM:
PUSH PSW
1012 F5
SUI 20H
1013 D6
STA 2020H
1015
POP PSW
1018 F1
RET
1019 C9
EXIT:
HLT
101A 76 5
ORG 2000H
2000 FF
DATA1:
DFB FFH,22H,33H
2001 22
RESULT:
DFS 1
2002 33 52
114
2003
Crystal
3Mhz
Tstate
1/(.5x3E6)
E-07 s
Total1
52x6.67E-7
E-05
34.667 ms
Total2
114x6.67E-7
76.000
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4. Interrupts
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5. What is an Interrupt ?
A hardware interrupt is a CPU facility which permits spurious asynchronous events to suspend program execution and instead execute a software module to service the event.
The connection to the processor which allows external devices to signal a request for service is called an interrupt pin.
The software module that the processor executes in response to an interrupt is called an interrupt service routine ( ISR ).
The interrupt mechanism is such that after completion of the ISR the processor returns to execution of the main program from the point at which it was interrupted.
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6. Interrupt Event Sequence
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7. Direct and Vectored Interrupts
With direct interrupts, the interrupting device need to provide the interrupt signal only. i.e. to assert the signal to the interrupt pin of the processor.
With direct interrupts the address of the first instruction of the ISR for the particular interrupt is pre-programmed into the CPU.
With vectored interrupts the interrupting device has to supply both the interrupt signal and the 16-bit address of the first instruction of the ISR.
Interrupt service routines for vectored interrupts can reside anywhere in the memory map of the computer system.
There are 3 categories
Direct interrupt (non-vectored)
Vectored Intterrupt
Maskable Interrupt
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8. Maskable and Non-maskable Interrupts
A non-maskable interrupt will always, if asserted, interrupt the processor. There is no software mechanism to prevent the processor being interrupted by a non-maskable interrupt.
A maskable interrupt, if asserted, will only interrupt the processor if it is enabled ( unmasked ). Maskable interrupts can be enabled ( unmasked ) or disabled ( masked ) by software.
Most maskable interrupts automatically become disabled (masked) after an interrupt has occurred. It requires further software commands to re-enable maskable interrupts.
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9. Interrupt Priority
For processor with multiple interrupt input pins, the various interrupts are assigned a priority.
When simultaneous interrupts occur the highest priority interrupt will be serviced before lower priority interrupts.
It is possible to arrange software such that whilst a lower priority interrupt is being serviced that a higher priority interrupt can interrupt the lower priority service routine.
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10. 8085A Interrupts
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11. Interrupt Trigger Type Trap Rising Edge AND High Level RST 7
Interrupt Trigger Type Trap Rising Edge AND High Level RST 7.5 Rising Edge RST 6.5 High Level RST 5.5 High Level INTR High Level
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12. Enabling and Disabling Maskable Interrupts
The DI (disable interrupts) instruction disables all maskable interrupts.
The EI (enable interrupts) instruction enables the vectored interrupt INTR and the unmasked restart interrupts RST 5.5, RST 6.5 and RST 7.5.
The interrupt mask for the restart interrupts is determined by the contents of the accumulator when the SIM instruction is executed.
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13. EXAMPLE (Enable/Disable Direct Interrupt)
For example to disable mask RST 7.5 and RST 5.5 and enable mask RST6.5 MVI A, B SIM ;Set Interrupt Mask EI ;Enable Interrupt
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14. ORG 0000H JMP START ORG 0034H JMP ISR65 ORG 003CH JMP ISR75 START: …
ORG 0000H JMP START ORG 0034H JMP ISR65 ORG 003CH JMP ISR75 START: …. MVI A, B SIM EI ….. ISR65: ….. RET ISR75: …..
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15. Machine Cycles with Direct Interrupts
Since there is no requirement to supply ISR addresses with direct interrupts ( TRAP, RST 5.5, RST 6.5 & RST 7.5 ) then there is no requirement for the 8085A to execute INTA machine cycles in response to such interrupts.
However to provide the CPU sufficient time to process a direct interrupt a six T-state bus idle machine cycle is introduced, following recognition of the direct interrupt.
During the bus idle machine cycle no control signal is asserted nor is the program counter incremented. Ready line control is ignored during the bus idle cycle.
Following the bus idle cycle two memory write cycles are executed to save the save current contents of the program counter on the stack.
The program counter is then overwritten with the pre-programmed address for the particular interrupt source.
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16. Machine Cycles with Direct Interrupts
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17. Discussion of example
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18. Machine Cycles with Vectored Interrupts
The 8085A processor executes a number of machine cycles, in response to a vectored interrupt (intr), prior to execution of the first instruction of the interrupt service routine.
The processor completes the execution of the current instruction. (Note : The processor only samples the interrupt inputs in the last T-state of the last machine cycle in the current instruction cycle)
This has implication in system design as it means that the interrupt signal on INTR must remain in the asserted state for at least the longest instruction in the 8085A instruction set to guarantee that the processor recognises the interrupt.
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19. Machine Cycles with Vectored Interrupts
The processor then executes a six T-state interrupt acknowledge machine cycle ( the INTA machine cycle is similar to the opcode fetch machine cycle except that the program counter is not incremented and the INTA* control signal is asserted instead of RD*)
In response to the INTA* signal, the interrupting device need to place the opcode of an instruction onto the data bus ( called jamming ).
The processor reads the opcode in the normal manner and stores it in the instruction register.
The choice of opcode is restricted as it is necessary to automatically save the contents of the program counter to enable the program to return to the point in the software where it was interrupted.
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20. Example of Instruction Execution
The following are the sequence of operations the processor is required to perform to execute the instruction STA addr
Place program counter onto address bus ; opcode address
Assert control signal
Read opcode and load into instruction register ; PC incremented
Decode the opcode
Place program counter onto address bus ; address of byte 2
Read byte 2 and save in temp register W ; PC incremented
Place program counter onto address bus ; address of byte 3
Read byte 3 and save in temp register X ; PC incremented
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21. Machine Cycles with Vectored Interrupts (CALL)
The only viable choice of 8085A instruction is either the CALL instruction or the RST n instruction.
The CALL instruction is a 3-byte instruction with bytes 2 & 3 being the address of the first instruction of the subroutine ( in this case the interrupt service routine).
Following decoding of the call opcode, the processor executes a further two interrupt acknowledge machine cycles to fetch the address of the start of the ISR.
It is incumbent on the interrupting device to place the low byte of the address of the ISR onto the data bus in response to the second INTA* control signal and the high byte of the address in response to the third INTA* signal.
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22. Machine Cycles with Vectored Interrupts (CALL)
The execution phase of the CALL instruction can now take place.
The processor firstly executes two memory write machine cycles to save the current contents of the program counter onto the stack. The address as to where in memory the contents of PC is to be saved is specified by the stack pointer register.
Finally the processor overwrites the contents of the program counter with the second and third bytes of the call instruction.
The next instruction the processor will execute will be the first instruction of the ISR.
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23. Machine Cycles with Vectored Interrupts
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24. Machine Cycles with Vectored Interrupts
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25. Vector Interrupts (RST n)
The Restart instruction, RST n, where 0 ≤ n ≤ 7
RST n
((SP)-1)  (PCH)
((SP)-2)  (PCL)
((SP)  (SP) – 2
(PC)  8 * n
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26. Vector Interrupts (RST n)
In respond to the INTA strobe, external logic places an RST n opcode on the data bus.
RST n has the following bit pattern
11NNN111
where n=NNN (3 bit binary number) and restart address
is n * 8
For example if RST 1, NNN = 001 and restart address is 8
(RST 2 (address 10H), RST 3 (address 18H) etc)
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27. The 8085 recognizes 8 RESTART instructions: RST0 - RST7.
each of these would send the execution to a predetermined hard-wired memory location:
Restart Instruction
Equivalent to
RST0
CALL 0000H
RST1
CALL 0008H
RST2
CALL 0010H
RST3
CALL 0018H
RST4
CALL 0020H
RST5
CALL 0028H
RST6
CALL 0030H
RST7
CALL 0038H

28. Hardware Generation of RST Opcode
How does the external device produce the opcode for the appropriate RST instruction?
The opcode is simply a collection of bits.
So, the device needs to set the bits of the data bus to the appropriate value in response to an INTA signal.
Next example is for RST5 => CALL 0028H

29. Hardware Generation of RST Opcode
The following is an example of generating RST 5:
RST 5’s opcode is EF =
D D

30. RST instructions 8 RST instructions +5v EF to data bus Call Location 1
Mnemonics
Binary code
Hex
Call
Location D7 D6 D5 D4 D3 D2 D1 D0
RST0 1 C7
0000
RST1 CF
0008
RST2
0010
RST3 DF
0018
RST4 E7
0020
RST5 EF
0028
RST6 F7
0030
RST7 FF
0038
+5v 1 1
EF to data bus 1 1 1 1 1
Enable

31. Hardware Generation of RST Opcode
During the interrupt acknowledge machine cycle, (the 1st machine cycle of the RST operation):
The Microprocessor activates the INTA signal.
This signal will enable the Tri-state buffers, which will place the value EFH on the data bus.
Therefore, sending the Microprocessor the RST 5 instruction.
The RST 5 instruction is exactly equivalent to CALL 0028H

32. some appropriate delay between flash
Write a program to count continuously in binary with one second delay between each
Count. Service routine at XX70H to flash FFH five times when the interrupt occurs with
some appropriate delay between flash
Main program
Interrupt Service Routine
LXI SP, XX99H EI
MVI A, 00H
NXTCNT: OUT PORT1
MVI C, 01H
CALL DELAY
INR A
JMP NXTCNT
XX70:
SERV:
PUSH B
PUSH PSW
MVI B, 0AH
MVI A, 00H
FLASH:
OUT PORT1
MVI C, 01H
CALL DELAY
CMA
DCR B
JNZ FLASH
POP PSW
POP B EI
RET
Interrupt instr: EF
At 0028H JMP xx70H