CS161 – Design and Architecture of Computer Systems

CS161 – Design and Architecture of Computer Systems
Pipelined CPU Design

What we’ve learned so far
Instruction Set Architecture MIPS as our ISA throughout the course Single cycle execution Dis/Advantages? Multi cycle execution What next?

Can We Do Better? What limitations do you see with the multi-cycle design? Limited concurrency Some hardware resources are idle during different phases of instruction processing cycle “Fetch” logic is idle when an instruction is being “decoded” or “executed” Most of the datapath is idle when a memory access is happening

Can We Use the Idle Hardware to Improve Concurrency?
Goal: More concurrency  Higher instruction throughput (i.e., more “work” completed in one cycle) Idea: When an instruction is using some resources in its processing phase, process other instructions on idle resources not needed by that instruction E.g., when an instruction is being decoded, fetch the next instruction E.g., when an instruction is being executed, decode another instruction E.g., when an instruction is accessing data memory (ld/st), execute the next instruction E.g., when an instruction is writing its result into the register file, access data memory for the next instruction

Pipelining

Pipelining: Basic Idea
Divide the instruction processing cycle into distinct “stages” of processing Ensure there are enough hardware resources to process one instruction in each stage Process a different instruction in each stage Instructions consecutive in program order are processed in consecutive stages Benefit: Increases instruction processing throughput (1/CPI) Downside: Start thinking about this…

Example: Execution of Four Independent ADDs
Multi-cycle: 4 cycles per instruction Pipelined: 4 cycles per 4 instructions (steady state) F D E W F D E W F D E W F D E W Time F D E W F D E W Is life always this beautiful? F D E W F D E W Time

The Laundry Analogy - steps to do a load are sequentially dependent
“place one dirty load of clothes in the washer” “when the washer is finished, place the wet load in the dryer” “when the dryer is finished, take out the dry load and fold” “when folding is finished, ask your roommate (:D) to put the clothes away” - steps to do a load are sequentially dependent - no dependence between different loads - different steps do not share resources Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

Pipelining Multiple Loads of Laundry
- 4 loads of laundry in parallel - no additional resources - throughput increased by 4 - latency per load is the same Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

Pipelining Multiple Loads of Laundry: In Practice
the slowest step decides throughput Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

Morgan Kaufmann Publishers
24 June, 2019 Speedup of Pipelining k stages pipeline, t time per stage, n jobs Non-pipelined time = n*k*t Pipelined time = (k+n-1)*t This is an ideal case: No job depends on a previous job All jobs behave exactly the same Not realistic. Chapter 4 — The Processor

24 June, 2019 MIPS Pipeline Five stages, one step per stage IF: Instruction fetch from memory ID: Instruction decode & register read EX: Execute operation or calculate address MEM: Access memory operand WB: Write result back to register Chapter 4 — The Processor

Remember the Single-Cycle Uarch
PCSrc1=Jump PCSrc2=Br Taken bcond ALU operation Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

Dividing Into Stages Is this the correct partitioning?
200ps 100ps 200ps 200ps 100ps RF write Is this the correct partitioning? Why not 4 or 6 stages? Why not different boundaries? Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

24 June, 2019 Pipeline Performance Single-cycle (Tc= 800ps) 5-stage speedup is 4, not 5 as predicted by the ideal model. Why? Pipelined (Tc= 200ps) Chapter 4 — The Processor

24 June, 2019 Pipeline Speedup If all stages are balanced i.e., all take the same time If not balanced, speedup is less Speedup due to increased throughput Latency (time for each instruction) does not decrease Chapter 4 — The Processor

24 June, 2019 Pipeline Summary The BIG Picture Pipelining improves performance by increasing instruction throughput Executes multiple instructions in parallel Each instruction has the same latency Subject to hazards Structure, data, control Chapter 4 — The Processor

Enabling Pipelined Processing: Pipeline Registers
No resource is used by more than 1 stage! IRD PCF PCD+4 PCE+4 nPCM AE BE ImmE AoutM BM MDRW AoutW Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

Pipelined Operation Example
All instruction classes must follow the same path and timing through the pipeline stages. Any performance impact? Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

Pipelined Operation Example
Is life always this beautiful? Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

Illustrating Pipeline Operation: Operation View
MEM EX ID IF Inst4 WB t0 t1 t2 t3 t4 t5 Inst0 MEM EX ID IF Inst3 ID IF Inst1 EX ID IF Inst2 IF WB MEM WB EX MEM WB ID EX MEM IF ID EX IF ID steady state (full pipeline) IF

Control Points in a Pipeline
Identical set of control points as the single-cycle datapath!!

24 June, 2019 Hazards Situations that prevent starting the next instruction in the next cycle Structure hazards A required resource is busy: why we have I$ and D$ Data hazard Need to wait for previous instruction to complete its data read/write Control hazard Deciding on control action depends on previous instruction Chapter 4 — The Processor

24 June, 2019 Structure Hazards Conflict for use of a resource In MIPS pipeline with a single memory Load/store requires data access Instruction fetch would have to stall for that cycle Would cause a pipeline “bubble” Hence, pipelined datapaths require separate instruction/data memories Or separate instruction/data caches Chapter 4 — The Processor

24 June, 2019 Data Hazards An instruction depends on completion of data access by a previous instruction add $s0, $t0, $t1 sub $t2, $s0, $t3 Chapter 4 — The Processor

General framework of data hazards
Read After Write (RAW), true, or dataflow dependence i1: add r1, r2, r3 i2: add r4, r1, r5 Write After Read (WAR), anti dependence i2: add r2, r4, r5 Write After Write (WAW), output dependence i2: add r1, r4, r5

WAR & WAW WAR & WAW are name dependencies
Dependence is on the container’s name not on the value contained. Can be eliminated by renaming, static (in software) or dynamic (in hardware) WAW & WAR cannot occur in our pipeline All the instructions execute “in-order”

How to reduce the performance impact of RAW?
Morgan Kaufmann Publishers 24 June, 2019 How to reduce the performance impact of RAW? Forwarding (aka Bypassing): Use result when it is computed Don’t wait for it to be stored in a register Requires extra connections in the datapath Chapter 4 — The Processor

24 June, 2019 Load-Use Data Hazard Can’t always avoid stalls by forwarding If value not computed when needed Can’t forward backward in time! Chapter 4 — The Processor

Code Scheduling to Avoid Stalls
Morgan Kaufmann Publishers 24 June, 2019 Code Scheduling to Avoid Stalls Reorder code to avoid use of load result in the next instruction C code for A = B + E; C = B + F; Reordering is commonly done by modern compilers lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) stall stall 13 cycles 11 cycles Chapter 4 — The Processor

Data Hazards in ALU Instructions
Morgan Kaufmann Publishers 24 June, 2019 Data Hazards in ALU Instructions Consider this sequence: sub $2, $1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2) What happens when: Forwarding is supported Forwarding is not supported Chapter 4 — The Processor

Dependencies & Forwarding
Morgan Kaufmann Publishers 24 June, 2019 Dependencies & Forwarding Forwarding Chapter 4 — The Processor

Control Dependence Question: What should the fetch PC be in the next cycle? Answer: The address of the next instruction All instructions are control dependent on previous ones. Why? If the fetched instruction is a non-control-flow instruction: Next Fetch PC is the address of the next-sequential instruction Easy to determine if we know the size of the fetched instruction If the instruction that is fetched is a control-flow instruction: How do we determine the next Fetch PC? In fact, how do we know whether or not the fetched instruction is a control-flow instruction?

How to Handle Control Dependences
Critical to keep the pipeline full with correct sequence of dynamic instructions. Potential solutions if the instruction is a control-flow instruction: Stall the pipeline until we know the next fetch address Guess the next fetch address (branch prediction) Employ delayed branching (branch delay slot) Do something else (fine-grained multithreading)

Stall Fetch Until Next PC is Available: Good Idea?
IF t0 t1 t2 t3 t4 t5 Insti Instj Instk Instl Insth ID IF t0 t1 t2 t3 t4 t5 Insti Instj Instk Instl Insth ID ALU MEM WB IF t0 t1 t2 t3 t4 t5 Insti Instj Instk Instl Insth ID ALU MEM WB IF t0 t1 t2 t3 t4 t5 Insti Instj Instk Instl Insth ID ALU MEM IF t0 t1 t2 t3 t4 t5 Insti Instj Instk Instl Insth ID ALU MEM WB IF t0 t1 t2 t3 t4 t5 Insti Instj Instk Instl Insth ID ALU t0 t1 t2 t3 t4 t5 Insth IF Insti Instj Instk Instl This is the case with non-control-flow and unconditional br instructions!

Doing Better than Stalling Fetch …
Rather than waiting for true-dependence on PC to resolve, just guess nextPC = PC+4 to keep fetching every cycle Is this a good guess? What do you lose if you guessed incorrectly? ~20% of the instruction mix is control flow ~50 % of “forward” control flow (i.e., if-then-else) is taken ~90% of “backward” control flow (i.e., loop back) is taken Overall, typically ~70% taken and ~30% not taken [Lee and Smith, 1984] Expect “nextPC = PC+4” ~86% of the time, but what about the remaining 14%?

Delayed Branching (I) Change the semantics of a branch instruction
Branch after N instructions Branch after N cycles Idea: Fill the delay slot with a useful instruction in order to avoid stalling the pipeline! Problem: How do you find instructions to fill the delay slots? Branch must be independent of delay slot instructions Unconditional branch: Easier to find instructions to fill the delay slot Conditional branch: Condition computation should not depend on instructions in delay slots  difficult to fill the delay slot

Delayed Branching (II)
Normal code: Timeline: Delayed branch code: Timeline: A A if ex if ex B C C A BC X A BC X B A B C A BC C D C B D E BC C E B BC F -- BC F G B X: G G -- X: G 6 cycles 5 cycles

An Aside: Filling the Delay Slot
reordering data independent (RAW, WAW, WAR) instructions does not change program semantics Safe? For correctness: add a new instruction to the not-taken path? For correctness: add a new instruction to the taken path? within same basic block [Based on original figure from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

Fine-Grained Multithreading
Idea: Hardware has multiple thread contexts. Each cycle, fetch engine fetches from a different thread. By the time the fetched branch/instruction resolves, no instruction is fetched from the same thread Branch/instruction resolution latency overlapped with execution of other threads’ instructions + No logic needed for handling control and data dependences within a thread -- Single thread performance suffers -- Extra logic for keeping thread contexts -- Does not overlap latency if not enough threads to cover the whole pipeline Latency overlap/hiding

Fine-grained Multithreading (II)
Idea: Switch to another thread every cycle such that no two instructions from a thread are in the pipeline concurrently Tolerates the control and data dependency latencies by overlapping the latency with useful work from other threads Improves pipeline utilization by taking advantage of multiple threads

Branch Prediction

Branch Prediction: Guess the Next Instruction to Fetch
PC 0x0004 0x0008 0x0007 0x0005 0x0006 ?? I-$ DEC RF WB 0x0001 LD R1, MEM[R0] 0x0002 D-$ ADD R2, R2, #1 0x0003 BRZERO 0x0001 0x0004 ADD R3, R2, #1 12 cycles 0x0005 MUL R1, R2, R3 0x0006 LD R2, MEM[R2] Branch prediction 0x0007 LD R0, MEM[R2] 8 cycles

Misprediction Penalty
PC Flush!! I-$ DEC RF WB 0x0001 LD R1, MEM[R0] 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002 D-$ ADD R2, R2, #1 0x0003 BRZERO 0x0001 0x0004 ADD R3, R2, #1 0x0005 MUL R1, R2, R3 0x0006 LD R2, MEM[R2] 0x0007 LD R0, MEM[R2]

Branch Prediction Processors are pipelined to increase concurrency
How do we keep the pipeline full in the presence of branches? Guess the next instruction when a branch is fetched Requires guessing the direction and target of a branch A Branch condition, TARGET B1 B3 Pipeline Fetch Decode Rename Schedule RegisterRead Execute D B1 A B1 A D E F B1 A D E F B1 A D E F B3 B1 A D E F B1 A D E F B1 A D E F B1 A D E F B1 A D E F B1 A D A B1 A D E B1 A D E F E What to fetch next? Target Misprediction Detected! Flush the pipeline Fetch from the correct target Verify the Prediction F

Branch Prediction: Always PC+4
IFPC+4 IFPC t0 t1 t2 t3 t4 t5 Insti Instj Instk Instl Insth ID ALU IFPC+8 IFtarget MEM IFPC+4 IFPC t0 t1 t2 t3 t4 t5 Insti Instj Instk Instl Insth ID ALU IFPC+8 Insth branch condition and target evaluated in ALU IFPC t0 t1 t2 t3 t4 t5 Insti Instj Instk Instl Insth When a branch resolves - branch target (Instk) is fetched - all instructions fetched since insth (so called “wrong-path” instructions) must be flushed Insth is a branch

Pipeline Flush on a Misprediction
Insth IFPC ID ALU MEM ID IF WB Insti IFPC+4 ID killed Instj IFPC+8 killed Instk IFtarget ALU ID IF WB Instl Insth is a branch

Performance Analysis correct guess  no penalty ~86% of the time
incorrect guess  2 bubbles Assume no data dependency related stalls 20% control flow instructions 70% of control flow instructions are taken CPI = [ 1 + (0.20*0.7) * 2 ] = = [ * 2 ] = 1.28 probability of a wrong guess penalty for a wrong guess Can we reduce either of the two penalty terms?

Reducing Branch Misprediction Penalty
Resolve branch condition and target address early Is this a good idea? CPI = [ 1 + (0.2*0.7) * 1 ] = 1.14 [Based on original figure from P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]

Branch Prediction (Enhanced)
Idea: Predict the next fetch address (to be used in the next cycle) Requires three things to be predicted at fetch stage: Whether the fetched instruction is a branch Branch direction (actual branch prediction, taken/not taken?) Branch target address (if taken) Observation: Target address remains the same for a conditional direct branch across dynamic instances Idea: Store the target address from previous instance and access it with the PC Called Branch Target Buffer (BTB) or Branch Target Address Cache

Fetch Stage with BTB and Direction Prediction
Direction predictor (taken?) taken? PC + inst size Next Fetch Address Program Counter hit? Address of the current branch target address Cache of Target Addresses (BTB: Branch Target Buffer) Always taken CPI = [ 1 + (0.20*0.3) * 2 ] = (70% of branches taken)

Three Things to Be Predicted
Requires three things to be predicted at fetch stage: 1. Whether the fetched instruction is a branch 2. Branch direction (taken/not taken?) 3. Branch target address (if taken) Third (3.) can be accomplished using a BTB Remember target address computed last time branch was executed First (1.) can be accomplished using a BTB If BTB provides a target address for the program counter, then it must be a branch Second (2.): How do we predict the direction?

Simple Branch Direction Prediction Schemes
Compile time (static) Always not taken Always taken BTFN (Backward taken, forward not taken) Profile based (likely direction) Programmer based Run time (dynamic) Last time prediction (single-bit) double-bit prediction

Static Branch Prediction (I)
Always not-taken Simple to implement: no need for BTB, no direction prediction Low accuracy: ~30-40% (for conditional branches) Always taken No direction prediction Better accuracy: ~60-70% (for conditional branches) Backward branches (i.e. loop branches) are usually taken Backward branch: target address lower than branch PC Backward taken, forward not taken (BTFN) Predict backward (loop) branches as taken, others not-taken

Static Branch Prediction (II)
Profile-based Idea: Compiler determines likely direction for each branch using a profile run. Encodes that direction as a hint bit in the branch instruction format. + Per branch prediction (more accurate than schemes in previous slide)  accurate if profile is representative! -- Requires hint bits in the branch instruction format -- Accuracy depends on dynamic branch behavior: TTTTTTTTTTNNNNNNNNNN  50% accuracy TNTNTNTNTNTNTNTNTNTN  50% accuracy -- Accuracy depends on the representativeness of profile input set

Static Branch Prediction (III)
Programmer-based Idea: Programmer provides the statically-predicted direction Via pragmas in the programming language that qualify a branch as likely-taken versus likely-not-taken + Does not require profiling or program analysis + Programmer may know some branches and their program better than other analysis techniques -- Requires programming language, compiler, ISA support -- Burdens the programmer?

Pragmas Idea: Keywords that enable a programmer to convey hints to lower levels of the transformation hierarchy if (likely(x)) { ... } if (unlikely(error)) { … }

Dynamic Branch Prediction
Idea: Predict branches based on dynamic information (collected at run-time) Advantages + Prediction based on history of the execution of branches + It can adapt to dynamic changes in branch behavior + No need for static profiling: input set representativeness problem goes away Disadvantages -- More complex (requires additional hardware)

Last Time Predictor Last time predictor
Single bit per branch (stored in BTB) Indicates which direction branch went last time it executed TTTTTTTTTTNNNNNNNNNN  90% accuracy Always mispredicts the last iteration and the first iteration of a loop branch Accuracy for a loop with N iterations = (N-2)/N + Loop branches for loops with large N (number of iterations) -- Loop branches for loops will small N (number of iterations) TNTNTNTNTNTNTNTNTNTN  0% accuracy Last-time predictor CPI = [ 1 + (0.20*0.15) * 2 ] = (Assuming 85% accuracy)

State Machine for Last-Time Prediction
actually taken predict taken predict not taken actually taken actually not taken actually not taken

Improving the Last Time Predictor
Problem: A last-time predictor changes its prediction from TNT or NTT too quickly even though the branch may be mostly taken or mostly not taken Solution Idea: Add hysteresis to the predictor so that prediction does not change on a single different outcome Use two bits to track the history of predictions for a branch instead of a single bit Can have 2 states for T or NT instead of 1 state for each

Two-Bit Counter Based Prediction
Each branch associated with a two-bit counter One more bit provides hysteresis A strong prediction does not change with one single different outcome Accuracy for a loop with N iterations = (N-1)/N TNTNTNTNTNTNTNTNTNTN  50% accuracy (assuming counter initialized to weakly taken) + Better prediction accuracy -- More hardware cost (but counter can be part of a BTB entry) 2BC predictor CPI = [ 1 + (0.20*0.10) * 2 ] = (90% accuracy)

Hysteresis Using a 2-bit Counter
“weakly taken” “strongly !taken” actually !taken actually taken pred taken pred taken actually !taken taken actually taken actually !taken pred !taken pred !taken Change prediction after 2 consecutive mistakes

Is This Good Enough? ~85-90% accuracy for many programs with 2-bit counter based prediction (also called bimodal prediction) Is this good enough? How big is the branch problem?

Rethinking the The Branch Problem
Control flow instructions (branches) are frequent 15-25% of all instructions Problem: Next fetch address after a control-flow instruction is not determined after N cycles in a pipelined processor N cycles: (minimum) branch resolution latency If we are fetching W instructions per cycle (i.e., if the pipeline is W wide) A branch misprediction leads to N x W wasted instruction slots

Importance of The Branch Problem
Assume N = 20 (20 pipe stages), W = 5 (5 wide fetch) Assume: 1 out of 5 instructions is a branch Assume: Each 5 instruction-block ends with a branch How long does it take to fetch 500 instructions? 100% accuracy 100 cycles (all instructions fetched on the correct path) No wasted work 99% accuracy 100 (correct path) + 20 (wrong path) = 120 cycles 20% extra instructions fetched 98% accuracy 100 (correct path) + 20 * 2 (wrong path) = 140 cycles 40% extra instructions fetched 95% accuracy 100 (correct path) + 20 * 5 (wrong path) = 200 cycles 100% extra instructions fetched

CS161 – Design and Architecture of Computer Systems

Similar presentations

Presentation on theme: "CS161 – Design and Architecture of Computer Systems"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

CS161 – Design and Architecture of Computer Systems

Similar presentations

Presentation on theme: "CS161 – Design and Architecture of Computer Systems"— Presentation transcript:

Similar presentations

About project

Feedback