1. The Trigger Control System of the CMS Level-1 Trigger
CentralTrigger Control TCS board
FDL
8 FinalOR
FMM
TTCci
crate
L1A, BGo commands
STATUS SIGNALS
LHC interface
BC0 and CLK
Distribution
Detector Partition
32 PARTITIONS
L1A record
Status Signals
ORBIT
CLK
EVENT MANAGER
8 DAQ-Partitions
aTTS 8
TIM
CLK,BCR
BC0
EMULATOR
Signals to EMU‘s
Tracker Partition
Global Trigger Crate
reduce 40 MHz of bunch crossings to data taking rate
--> 100 kHz: L1-trigger (hardware)
--> 100 Hz: High-Level trigger (computer farm)
L1 trigger decision calculated in “Global Trigger Logic”

2. The Trigger Control System of the CMS Level-1 Trigger
The Central Trigger Control system is implemented in a 9U VME module
logic implemented in Field Programmable Gate Arrays (FPGAs)
Xilinx type
input data arrive via several ancillary modules