1. Sequential Design
תרגול 10

2. Y86 Processor Simulator
The Computer Simulation of a Central Processing Unit Based on the Intel IA32, or X86, Instruction Set.
תמר שרוט, נועם חזון

3. Y86 Instruction Set Byte 1 2 3 4 5 nop addl 6 subl 1 andl 2 xorl 31 2 3 4 5
nop
addl 6
subl 1
andl 2
xorl 3
halt 1
rrmovl rA, rB 2 rA rB
irmovl V, rB 3 8 rB V
rmmovl rA, D(rB) 4 rA rB D
jmp 7
jle 1 jl 2 je 3
jne 4
jge 5 jg 6
mrmovl D(rB), rA 5 rA rB D
OPl rA, rB 6 fn rA rB
jXX Dest 7 fn
Dest
call Dest 8
Dest
ret 9
pushl rA A rA 8
popl rA B rA 8

4. Tracing the execution of SEQ

5. Six Stages
Fetch - Reads the command bytes from memory using the PC. Extracts icode and ifun and if needed fills rA, rB and valC. Also calculates valP = length(instruction) + PC.
Decode - Reads two values from registers and inserts them into valA and valB.
Execute - According to the ifun either the ALU executes the command or calculates the new stack pointer. The result will be put into valE. For a jump instruction checks condition codes and branch conditions.
Memory - Reads or writes from memory. The value will be put into ValM.
Write Back - Writes up to two results into the registers.
PC Update - Now updates the PC for the next command.

6. subl, line 3

7. irmovl, line 4

8. pushl, line 6

9. popl, line 7

10. SEQ Hardware Key Blue boxes: predesigned hardware blocks Gray boxes:
E.g., memories, ALU
Gray boxes:
control logic
Describe in HCL
White ovals: labels for signals
Thick lines:
32-bit word values
Thin lines:
4-8 bit values
Dotted lines:
1-bit values

11. Is this equivalent to our tables?
Explicit control over sequencing, PC CC
Date memory
Register file
The key idea: The processor never needs to read back the state updated by an instruction in order to complete the processing of this instruction!
Examples:
Pushl does not use the updated %esp
No operation set and read the Condition Codes

12. Handling ambiguities What is the result of pushl %esp?
What is the result of popl %esp?
Which port will get priority in popl?