1. ELEC 7770 Advanced VLSI Design Spring 2010 Zero-Skew Clock Routing
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

2. Zero-Skew Clock RoutingFF FF FF FF FF FF FF FF CK FF FF FF FF FF FF FF FF
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

3. Zero-Skew: References
H-Tree
A. L. Fisher and H. T. Kung, “Synchronizing Large Systolic Arrays,” Proc. SPIE, vol. 341, pp , May 1982.
A. Kahng, J. Cong and G. Robins, “Hig-Performance Clock Routing Based on Recursive Geomrtric Matching,” Proc. Design Automation Conf., June 1991, pp
M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock Routing for High-Performance IC’s,” Proc. Design Automation Conf., June 1990, pp
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

4. ELEC 7770: Advanced VLSI Design (Agrawal)
Zero-Skew Routing
Build clock tree bottom up:
Leaf nodes are all equal loading flip-flops.
Two zero-skew subtrees are joined to form a larger zero-skew subtree.
Entire clock tree is built recursively.
R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” IEEE Trans. CAD, vol. 12, no. 2, pp , Feb
J. Rubenstein, P. Penfield and M. A. Horowitz, “Signal Delay in RC Tree Networks,” IEEE Trans. CAD, vol. 2, no. 3, pp , July 1983.
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

5. ELEC 7770: Advanced VLSI Design (Agrawal)
Balancing Subtrees (1) xL r1 A t1
c1/2
c1/2 C1
Subtree 1
Tapping point
(1 – x)L r2 B t2
c2/2
c2/2 C2
Subtree 2
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

6. ELEC 7770: Advanced VLSI Design (Agrawal)
Balancing Subtrees (2)
Subtrees 1 and 2 are each balanced (zero-skew) trees, with delays t1 and t2 to respective leaf nodes.
Total capacitances of subtrees are C1 and C2, respectively.
Connect points A and B by a minimum-length wire of length L.
Determine a tapping point x such that wire lengths xL and (1 – x)L produce zero skew.
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

7. ELEC 7770: Advanced VLSI Design (Agrawal)
Balancing Subtrees (3)
Use Elmore delay formula:
0.69 r1(C1 + c1/2) + t1 = 0.69 r2(C2 + c2/2) + t2
Substitute:
r1 = axL, r2 = a(1 – x)L
c1 = bxL, c2 = b(1 –x)L
abL2x + aL(C1+C2)x = 1.45 (t2 – t1) + aL(C2+bL/2)
Then solve for x:
1.45 (t2 – t1) + aL (C2 + bL/2)
x = ───────────────────
aL(bL + C1 + C2)
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

8. Balancing Subtrees Example 1
Subtree parameters:
Subtree 1: t1 = 5ps, C1 = 3pF
Subtree 2: t2 = 10ps, C2 = 6pF
Interconnect:
L = 1mm
Wire parameters: a = 100Ω/cm, b = 1pF/cm
Tapping point:
1.45(t2 – t1) + aL (C2 + bL/2) 1.45(10–5) + 100×0.1(6 + 1×0.1/2)
X = ────────────────── = ──────────────────────
aL (bL + C1 + C2) ×0.1(1× )
= 1.45( )/(10×9.1) =
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

9. ELEC 7770: Advanced VLSI Design (Agrawal)
Example 1 FF
t1 = 5ps, C1 = 3pF FF mm
Subtree 1 FF FF
To next
level FF
0.2555mm
t2 = 10ps, C2 = 6pF FF
Subtree 2 FF
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

10. Balancing Subtrees, x > 1
Tapping point set at root of tree with larger loading (C2, t2).
Wire to the root of other tree is elongated to provide additional delay. Wire length L is found as follows:
Set x = 1 in abL2x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2)
i.e., L2 + (2C1/b)L – 2.9 (t2 – t1)/(ab) = 0
Wire length is given by:
[(aC1) ab(t2 – t1)]½ – aC1
L = ────────────────────
a b
R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” IEEE Trans. CAD, vol. 12, no. 2, pp , Feb
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

11. Balancing Subtrees Example 2
Subtree parameters:
Subtree 1: t1 = 2ps, C1 = 1pF
Subtree 2: t2 = 15ps, C2 = 10pF
Interconnect:
L = 1mm
Wire parameters: a = 100Ω/cm, b = 1pF/cm
Tapping point:
1.45(t2 – t1) + aL (C2 + bL/2) 1.45(15–2) + 100×0.1(10 + 1×0.1/2)
x = ─────────────────── = ──────────────────────
aL (bL + C1 + C2) ×0.1(1× )
= ( )/(10×11.1) =
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

12. ELEC 7770: Advanced VLSI Design (Agrawal)
Example 2, x =
Setting x = 1.0,
[(aC1)2+2.9ab(t2 – t1)]½ – aC1
L = ────────────────────
a b
[(100×1) (15 – 2)]½ – 100×1
= ───────────────────────
100×1
= cm
For a wire of 1.735mm length, place the clock feed at one end.
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

13. ELEC 7770: Advanced VLSI Design (Agrawal)
Example 2, L = 1.735mm FF
t1 = 2ps, C1 = 1pF FF
Subtree 1 FF
L = mm FF FF
To next
level
t2 = 15ps, C2 = 10pF FF
Subtree 2 FF
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

14. Balancing Subtrees, x < 0
Tapping point set at root of tree with smaller loading (C1, t1).
Wire to the root of other tree is elongated to provide additional delay. Wire length L found as follows:
Set x = 0 in abL2x + aL(C1+C2)x = 1.45(t2 – t1)+aL(C2+bL/2)
i.e., L2 + (2C2/b)L – 2.9 (t1 – t2)/(ab) = 0
Wire length is given by:
[(aC2) ab(t1 – t2)]½ – aC2
L = ────────────────────
a b
R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” IEEE Trans. CAD, vol. 12, no. 2, pp , Feb
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

15. Balancing Subtrees Example 3
Subtree parameters:
Subtree 1: t1 = 15ps, C1 = 10pF
Subtree 2: t2 = 2ps, C2 = 1pF
Interconnect:
L = 1mm
Wire parameters: a = 100Ω/cm, b = 1pF/cm
Tapping point:
1.45(t2 – t1) + aL (C2 + bL/2) 1.45(2–15) + 100×0.1(1 + 1×0.1/2)
x = ─────────────────── = ──────────────────────
aL (bL + C1 + C2) ×0.1(1× )
= ( – )/(10×11.1) = –
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

16. ELEC 7770: Advanced VLSI Design (Agrawal)
Example 3, x = –
Setting x = 0.0,
[(aC2)2+2.9ab(t1 – t2)]½ – aC2
L = ──────────────────
a b
[(100×1)2+290 (15 – 2)]½ – 100×1
= ───────────────────────
100×1
= cm
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

17. ELEC 7770: Advanced VLSI Design (Agrawal)
Example 3, L = 1.255mm FF FF
To next
level
t1 = 15ps, C1 = 10pF FF FF
L = 1.735mm
Subtree 1 FF
t2 = 2ps, C2 = 1pF FF
Subtree 2 FF
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

18. ELEC 7770: Advanced VLSI Design (Agrawal)
Zero-Skew Design
Delay
=75ns
Delay
= 50ns
FF A
Comb.
FF B
Comb.
FF C CK CK
time
Tck = 75ns
Single-cycle path delay
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

19. ELEC 7770: Advanced VLSI Design (Agrawal)
Nonzero-Skew Design
Delay
=75ns
Delay
= 50ns
FF A
Comb.
FF B
Comb.
FF C CK
Delay = 25ns CK
time
Tck = 50ns
Single-cycle path delay
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)

20. ELEC 7770: Advanced VLSI Design (Agrawal)
Conclusion
Zero-skew design is possible at the layout level.
Zero-skew usually results in higher clock speed.
Nonzero clock skews can improve the design with reduced hardware and/or higher speed.
Spring 2010, Mar 5
ELEC 7770: Advanced VLSI Design (Agrawal)