1. Advanced Computer Architecture Lecture 10
Project 3 reviews
Project 4 introduction
DMA controller
Lillevik s06-l10
University of Portland School of Engineering

2. Project 3 team reviews Team Cat Team Dog Lillevik 437s06-l10
University of Portland School of Engineering

3. Project 4 overview
Objective: design a round-robin arbiter for a four-CPU system
System
Contains four unique CPU models (CPU0, CPU1, CPU2, CPU3) and programs (pgm0, pgm1, pgm2, pgm3)
Four bus requests (Breq0, Breq1, Breq2, Breq3)
Four bus grants (Bgnt0, Bgnt1, Bgnt2, Bgnt3)
Lillevik s06-l10
University of Portland School of Engineering

4. Project 4 system Arbiter Lillevik 437s06-l10
University of Portland School of Engineering

5. Arbiter similar to Grey code counter
Project 4 state diagram 00 10 11 01 G B C D E F H A
Arbiter similar to Grey code counter
Lillevik s06-l10
University of Portland School of Engineering

6. Each CPU writes to Port 10, twice
Project 4 program
CPU0
NOTE: Addresses 0, 1 code will change for each CPU
EXAMPLE: CPU 3 will execute 0xa1003
nop
Each CPU writes to Port 10, twice
Lillevik s06-l10
University of Portland School of Engineering

7. Find expected behavior?
Zero gets bus first
Writes 0 into Port 10
CPU 1 gets bus, writes 1 to Port 10
CPU 3
CPU 2
Lillevik s06-l10
University of Portland School of Engineering

8. Project 4 trace Lillevik 437s06-l10
University of Portland School of Engineering

9. Hard drive DMA Assumptions Initialization commands
Project 5
Assumptions
Operation: Input, or read disk, or read file
HD buffer: represent with a ROM
Initialization commands
Port 1: start address
Port 2: word count
Port 4: start
Design contains 5 sections
Lillevik s06-l10
University of Portland School of Engineering

10. DMA hardware view n words adr X adr X+(n-1) Memory I/O device buffer
System bus
adr 0
adr (n-1)
Lillevik s06-l10
University of Portland School of Engineering

11. HD system schematic Lillevik 437s06-l10
University of Portland School of Engineering

12. Memory schematic Lillevik 437s06-l10
University of Portland School of Engineering

13. DMA controller architecture
Word
Count
Data
Buffer
Memory
Address
Control D A C
Xcvr
Counts up from zero
Counts down to zero
Preset counter
Lillevik s06-l10
University of Portland School of Engineering

14. BA counts from zero up to N-1
Buffer address block
Buffer
Address
BAclr
BAdr
BAinc
BA counts from zero up to N-1
Lillevik s06-l10
University of Portland School of Engineering

15. Data buffer block BAdr Data Buffer (ROM) Data Ben Lillevik 437s06-l10
University of Portland School of Engineering

16. WC counts down from N-1 to zero
Word count block
Word
Count
WCload
WCdec
Zero
Data
WC counts down from N-1 to zero
Lillevik s06-l10
University of Portland School of Engineering

17. MA counts up from X to X+(N-1)
Memory address block
Memory
Address
MAload
MAinc
Ben A D
MA counts up from X to X+(N-1)
Lillevik s06-l10
University of Portland School of Engineering

18. Updated block diagram Data Buffer Word Memory Count Address Xcvr D
one section
Word
Count
Data
Buffer
Memory
Address
Control D A C
Xcvr
Port1
Port2
BAclr
BAinc
WCdec
MAinc
Zero
Ben
Lillevik s06-l10
University of Portland School of Engineering

19. Control section
Objective: decode the Port instructions, request bus, transfer data across the bus, coordinate the sequence of the other blocks, interrupt CPU when done
Role
Contains three subsections: decoder, counters, bus I/F
Bus I/F or FSM similar to CPU model
Lillevik s06-l10
University of Portland School of Engineering

20. Control 1: decode Objective: respond to CPU (I/O write) commands
Port 1: start address on D bus
Port 2: word count on D bus
Port 4: start (D bus ignored)
Role: create signals to load the MA counter, load WC counter, start DMA
Lillevik s06-l10
University of Portland School of Engineering

21. Control section block 1 Decode A Decode Port1 (MAload) Logic
Port2 (WCload) C
Port4 (Start)
Lillevik s06-l10
University of Portland School of Engineering

22. Control 2: counters
Objective: look for start signal, enter a sequence, repeat, stop when done (WC= =0)
Role: manipulate the three counters (buffer address, word count, memory address)
Lillevik s06-l10
University of Portland School of Engineering

23. Control section block 2 Counters Enables BAclr Start BAinc WCdec Zero
One signal?
Zero
MAinc
Lillevik s06-l10
University of Portland School of Engineering

24. Control 3: bus I/F
Objective: request the bus, drive the bus with data, generate interrupt when done
Role:
Generate a sequence of Breq, Bgnt, Ben, Ack
Drive the C, A, and D buses
Drive the Int line and wait for Inta
Lillevik s06-l10
University of Portland School of Engineering

25. Must drive C bus with memory write instruction
Control section block 3
Bus interface
Bus
I/F
Breq
Bgnt
Int
Ack
Ben
Inta C
Must drive C bus with memory write instruction
Lillevik s06-l10
University of Portland School of Engineering

26. Control input/outputs?
Lillevik s06-l10
University of Portland School of Engineering

27. HD DMA schematic Lillevik 437s06-l10
University of Portland School of Engineering

28. Lillevik s06-l10
University of Portland School of Engineering

29. Find expected behavior?
All CPU’s request the bus at the same time
Arbiter selects one CPU to own bus
Arbiter issues bus grants in sequence {0, 1, 3, 2}
First CPU to own bus depends on state of arbiter at that time
Lillevik s06-l10
University of Portland School of Engineering

30. Control input/outputs?
FSM
Clk, Reset
Breq
Bgnt
Zero
Count
Ben
Inta
Int
Port4
Clear
Ack
Lillevik s06-l10
University of Portland School of Engineering