1. NS Training Hardware

2. NS9750 LCD Block

3. Overview
The LCD Controller provides an interface to a STN or TFT LCD Panel. Display data is DMAed from external memory to the LCD controller.
To LCD Panel
LCD Controller
AHB BUS
(To Memory)

4. LCD Controller
Supports both monochrome and color, single- and dual-panel Super Twisted Nematic (STN) LCD panels
Supports 18 and 24-bit Thin Film Transistor (TFT) LCD color displays
STN mode supports up to 15 gray-levels for monochrome and 3375 colors
TFT mode supports up to 16M colors
Supports all popular display resolutions up to 1024x768 maximum
256 entry, 16-bit palette RAM
Monochrome STN supports 1,2, or 4 bits-per-pixel via palette RAM

5. LCD Controller
Color STN supports 1,2,4, or 8 bits-per-pixel via palette RAM
TFT supports 1,2,4,or 8 bits per-pixel via palette RAM; 16 and 24 bits per pixel direct
LCD timing programmable
AHB DMA engine transfers display data from external memory to dual 64x32 FIFOs
Supports big and little endian pixel format, as well as WinCE
LCD panel clock can either be generated internally from the AHB clock or provided via an external oscillator

6. LCD Controller Programmable Parameters
Horizontal front porch
Horizontal back porch
Horizontal sync pulse width
Number of pixels per line
Vertical front porch
Vertical back porch
Vertical sync pulse width
Number of lines per panel
Number of panel clocks per line
Signal polarity
AC panel bias
Panel clock frequency
Number of bits-per-pixel
Display type (STN mono/color or TFT)
STN 4 or 8 bit interface
STN dual or single panel
Pixel format (little-endian, big-endian or WinCE)
Interrupt generation event

7. LCD Panel Interface Signal Description CLPOWER LCD panel power enable
CLLP
Line sync pulse (STN) or horizontal sync pulse (TFT)
CLCP
LCD panel clock
CLFP
Frame pulse (STN) or vertical sync pulse (TFT)
CLAC
AC bias drive (STN) or data enable (TFT)
CLD[23:0]
LCD panel data
CLLE
Line end signal

8. LCD Setup Procedure
Setup horizontal timing parameters for LCD panel (e.g. front porch, back porch, sync width, number of pixels per line)
Setup vertical timing parameters for LCD panel (e.g. front porch, back porch, sync width, number of lines per panel)
Setup other display parameters (e.g. signal polarity, panel clock frequency, number of clocks per line)
Enable conditions that cause interrupt from LCD controller (e.g. vertical compare)
Setup base address in external memory of area to DMA display data from.

9. LCD Setup Procedure
Select clock source (AHB clock, AHB clock divided down, or external oscillator)
Load initial display data into external memory
Enable control signals to LCD panel by setting LcdEn bit.
System applies contrast voltage VEE
Apply power to LCD panel by setting LcdPwr bit. This drives CLPOWER active and enables CLD [23:0] to activate display. (see NS9750 Hardware Reference Manual for detailed description of power up and power down sequence)
Interrupts will occur during normal operation (e.g. during vertical sync). The application can use these to update the base address used for DMA (e.g. double buffered video display).

10. LCD Panel Clock Generation
Source of LCD panel clock is programmable via Clock Configuration Register in SCM
AHB clock divided by 1,2,4,8
External clock oscillator (LCDCLK) divided by 2
LCD controller provides an additional clock divider that can be used to divide the source clock further to generate the LCD panel clock (see NS9750 Hardware Reference Manual for programming limitations on clock divider value)

11. STN Displays’ Timing Diagrams
Vertical Timing
Horizontal Timing

12. TFT Displays’ Timing Diagrams
Vertical Timing
Horizontal Timing

13. Hints & Kinks
Can I directly directly connect the NS9750’s LCD interface signals to an LCD display panel?
Although there is nothing functionally wrong with this approach, the NS9750’s LCD outputs, with the exception of CLCP(8ma), are rated at only 4ma. Direct connection would only be practical over a few inches of trace. These drive strengths are definitely not applicable to driving a LCD panel via a cable. A single, low-skew, high drive buffer is recommended for applications requiring more drive than the NS9750 can provide. A single device with low-skew is required because the skew between the clock and all of the other signals is the key in meeting the timing requirements of the LCD panel.

14. Hints & Kinks
My 24-bit TFT LCD display panel requires differential inputs. How do I interface the NS9750 to it?
Most 24-bit TFT panels require LVDS (Low Voltage Differential Signaling) inputs. These typically require an off-the-shelf LVDS serializer device to interface the display controller to the display. The NS9750’s LCD interface can interface directly to the parallel interface of this serializer. Contact the manufacturer of the LCD display for a recommendation on which serializer device to use (e.g. National DS90C385)