1. Synchronous Digital Design Methodology and Guidelines
Digital System Design

2. Synchronous Design All flip-flops clocked by one common clock
Reset only used for initialization
Races and hazards are no problem

3. Synchronous Design Three things must be ensured by the designer:
Minimize and determine clock skew
Account for flip-flop setup and hold times
Reliably synchronize asynchronous inputs

4. Timing Analysis

5. Clock skew

6. Example
Determine the maximum frequency of the following circuit with and without skew

7. Clock Jitter

8. Clock Gating
Clock gating is done to disable the clock for low power consumption using a clken signal
It is wrong to gate the clock in the following way, instead use a synchronous load (enable) signal

9. Asynchronous Inputs
It is impossible to guarantee setup and hold timing constraints on inputs synchronized with a clock unrelated to the system clock

10. Asynchronous inputs
Synchronize only in one place

12. Metastability
Metastability is a phenomenon that may occur if the setup and hold time requirements of the FF are not met, leading in the output settling in an unknown value after unspecified time.

13. MTBF

14. Reliable synchronizer design

15. Multi-cycle synchronizer

16. Example
Design a synchronizer that synchronizes two inputs async1 and async2 generated with a 50 MHz clock CLK1, to a system with a 33 MHz clock CLK2 totally independent of CLK1. Draw appropriate timing diagrams.

17. Multi-cycle synchronizer with deskewing

18. Cascaded synchronizer

19. Example
Design a digital synchronizer to capture valid data according to the following timing diagram

20. Solution

21. Synchronizing high-speed data transfers
What happens when the asynchronous inputs are clocked faster than the system clock?

22. Case study: Ethernet receiver

23. Byte holding register

24. SCTRL circuit

25. Testing Basics
Defect: A difference between intended design and actual hardware
Error: A wrong output produced through a defect
Fault: A defect in a higher abstraction level

26. Example

27. Controllability and observability
Controllability: The difficulty of setting a specific signal to 0 or 1
Observability: The difficulty of reading a specific signal
Electron beam testing is too expensive
Must set signal through primary inputs and observe through primary outputs

28. Design For Testability (DFT)

29. Boundary scan
In boundary scan, all flip-flops enter a test mode where they are controllable and observable
After functional verification, normal flip-flops are replaced by scan flip-flops
Only D flip-flops must be used
Clocks must not be generated internally

30. Built-In Self-Test (BIST)