1. Progress on the 40 MHz SEU Test System based on DE2 Board
Feb. 01, 2010
In CPPM
By Zhao Lei

2. Test about the crosstalk from clock to psout signals from SEU chip to interface board
Waveform of the ‘psout’ signal of Channel 5
Waveform of the ‘psout’ signal of Channel 6

3. Test about the crosstalk from clock to psout signals from SEU chip to interface board
Waveform of the ‘psout’ signal of Channel 6 when 1 wire is used as ground line
Waveform of the ‘psout’ signal of Channel 6 when 2 wires are used as ground lines
After modification of the transmission of the clock signal

4. Long Time Test Results --Test Mode 0 : static test without read back

5. Long Time Test Results --Test Mode 0 (40 MHz , 2 hours)

6. Long Time Test Results --Test Mode 0 (160 kHz , 24 hours)

7. Long Time Test Results --Test Mode 1 : static test with read back

8. Long Time Test Results --Test Mode 1 (40 MHz , 2 hours)

9. Long Time Test Results --Test Mode 1 (160 kHz , 24 hours)

10. Long Time Test Results --Test Mode 2 : Test versus frequency based on latches

11. Long Time Test Results --Test Mode 2 (40 MHz , 2 hours)

12. Long Time Test Results --Test Mode 3 : Test versus frequency based on DFFs

13. Long Time Test Results --Test Mode 3 (40 MHz , 2 hours)

14. Waveform of the psout signals (blue) and error signal (red) in FPGA as for data pattern “11111” in Test mode 3

15. Waveform of the psout signals (blue) and error signal (red) in FPGA as for data pattern “00000” in Test mode 3

16. Conclusion
The crosstalk from the clock to psout signals could be greatly reduced by better shielding of ground.
From the long time test, the FPGA and software is approved to work well and stably in long time.
The system could run up to 40 MHz, and no errors occur for the first 3 test modes. Errors occur in test mode 3 with very low Bit Error Rate, which are probably due to ground, power supply or the electronic characteristics of the chips.

17. Thanks