1. WELCOME TO EE457 COMPUTER SYSTEMS ORGANIZATION

2. THREE MAIN TOPICS 1. CPU DESIGN 2. MEMORY SYSTEM 3. COMPUTER ARITHMETIC

3. CPU DESIGN MICRO-ARCHITECTURE DESIGN GENERAL DIGITAL SYSTEM DESIGN

4. MEMORY SYSTEM DESIGN CACHE + VIRTUAL MEMORY

5. COMPUTER ARITHMETIC 2’s Complement Arithmetic Review FAST ADDERS FAST MULTIPLIERS NON-LINEAR PIPELINES FOR ARTHMETIC OPERATIONS

6. COURSE PRE-REQUISITES EE201L INTRODUCTION TO DIGITAL CIRCUITS EE357 BASIC ORGANIZATION OF COMPUTER SYSTEMS

7. LECTURES & DISCUSSIONS LECTURES:. (a) 2:00-3:20PM MW OHE122
LECTURES & DISCUSSIONS LECTURES: (a) 2:00-3:20PM MW OHE (b) 4:00-5:20PM MW ZHS163 DISCUSSIONS: (a) 03:30-04:20PM Th ZHS252 (b) 12:00-12:50PM F OHE122

8. EXAMINATIONS (a) Quiz (~10%) Friday Feb
EXAMINATIONS (a) Quiz (~10%) Friday Feb. 22, : :45 AM PST (the quiz slot  extended by 40 min). (b) Midterm (~20%) Friday Apr. 5, : :45 AM PST (the quiz slot  extended by 40 min). (c) Final (~30%) Monday, May. 13, :30-4:20 PM PST (Common to both sections, Time extended by 50 min)

9. COURSE WEIGHTS Quiz. ~10% MIDTERM EXAM. ~20% HOMEWORKS
COURSE WEIGHTS Quiz ~10% MIDTERM EXAM ~20% HOMEWORKS % DESIGN PROJECTS % FINAL EXAM ~30%

10. LATE PENALTY HOMEWORKS:
LATE PENALTY HOMEWORKS: UP TO 5% PER DAY IF SOLUTION IS NOT DISTRIBUTED

11. LATE PENALTY LABS:. 2% PER DAY UP TO 7 DAYS
LATE PENALTY LABS: 2% PER DAY UP TO 7 DAYS 3% PER DAY AFTER 7 DAYS if specifically allowed The last lab may not have this much flexibility.

12. LECTURE CLASS ATTENDANCE PENALTY FOR MISSING:. 1% FOR 5TH, 6TH AND 7TH
LECTURE CLASS ATTENDANCE PENALTY FOR MISSING: 1% FOR 5TH, 6TH AND 7TH 2% FOR 8TH AND 9TH 4% FOR 10TH AND AFTER PENALTY FOR MISSING DISCUSSION CLASS: HALF OF LECTURE CLASS MISSING PENALTY % FOR 3rd, 4TH, 5TH, 6TH 1% FOR 7TH AND AFTER

13. REMOTE STUDENTS gandhi@usc.edu

14. DESIGN PROJECTS. PARTIALLY COMPLETE DESIGN FILES
DESIGN PROJECTS PARTIALLY COMPLETE DESIGN FILES Core design Verilog file: ~50% complete Testbench and wave.do files: ~80% to 100% complete TTL DATABOOK  NOT NECESSARY

15. Esperan Verilog Reference Guide
Is posted on the BB for personal use of USC faculty and students.

16. IEEE Verilog standard ieee-1364-2001 for USC library members only -- please do not distribute

17. HOMEWORK:. INDIVIDUAL EFFORT LAB:
HOMEWORK: INDIVIDUAL EFFORT LAB: (1) VERILOG CODING, SIMULATION AND DEBUGGING TEAM EFFORT (2) JUSTIFICATION, END-OF-LAB QUESTIONS INDIVIDUAL EFFORT

18. CLASS WEBPAGE DEN BLACKBOARD den. usc. edu https://www. uscden
CLASS WEBPAGE DEN BLACKBOARD den.usc.edu LEC / DIS WEBCASTS ASSIGNMENTS ANNOUNCEMENTS OFFICE HOURS

19. Verilog language and ModelSim Simulator INTRO. LECTUREs are posted

20. Buy these two items from the Bookstores (1) TEXTBOOK Computer Organization & Design - The Hardware and Software Interface 4th edition (Revised Printing) By D. A. Patterson (Berkeley) and J. L. Hennesy (Stanford) (2) CLASS NOTE CHAPTER 1 ON THE BLACK-BOARD ========================================= Lab Manual .pdf files will be posted progressively on the BB

21. Understand, No need to memorize, Learn to design
Understand, No need to memorize, Learn to design. Demonstrate your understanding in the exam ~40 hours of office hours per week

22. Grades

23. Grades
Very easy to get an A grade

24. Grades
Very easy to get an A grade
Equally easy to get a F grade

25. Grades
Very easy to get an A grade
Equally easy to get a F grade

26. We appreciate your efforts
~ 60% of the class gets an A grade
No place for the lazy and uninterested
~20% of the class fails or drops

27. There is no competition. Everyone can get an A grade
There is no competition. Everyone can get an A grade. You need to aspire for it, work for it. You get what you worked for. No grace grade (No minimum grade).