1. System Controller Approach
Oct 26, 2008
ECE Lecture 14 - System Controller

2. ECE 561 - Lecture 14 - System Controller
Lecture Overview
System Controller Approach
Using the system controller approach
Oct 26, 2008
ECE Lecture 14 - System Controller

3. ECE 561 - Lecture 14 - System Controller
General View
Partition the system into a main machine and submachines
Main machine is the coordinator
Submachines implement the tasks
Oct 26, 2008
ECE Lecture 14 - System Controller

4. ECE 561 - Lecture 14 - System Controller
For the Alarm Clock
Central view of the controller and subordinate state machines
Oct 26, 2008
ECE Lecture 14 - System Controller

5. ECE 561 - Lecture 14 - System Controller
Using VHDL
We can use VHDL to specify the interacting state machines
Each state machine is specified in VHDL using the state machine modeling methodology.
An entity specifying the inputs and outputs
An architecture with three process
Oct 26, 2008
ECE Lecture 14 - System Controller

6. ECE 561 - Lecture 14 - System Controller
Hierarchy
The top level controller (system controller) interacts and controls interaction among the state machines
It uses component instantiation to invoke each and connect them up
Oct 26, 2008
ECE Lecture 14 - System Controller

7. The declaration of the components
In the ARCHITECTURE of the controller
In the Declarative region declare the component
COMPONENT wigit
PORT(p1, p2 : IN BIT);
END COMPONENT;
This is identical to the ENTITY declaration for the component except that ENTITY is replaced by COMPONENT and there is no IS
Oct 26, 2008
ECE Lecture 14 - System Controller

8. ECE 561 - Lecture 14 - System Controller
The next step
Configure the component
Right after the component declaration configure the component
FOR C0 : wigit USE ENTITY work.wigit(one);
Now you are ready to use it
After the BEGIN
CO : wigit PORT MAP (A, B);
Oct 26, 2008
ECE Lecture 14 - System Controller

9. Signals to hook up units
Needing internal signals to connect signals of the state machines to each other and the controller
In the ARCHITECTURE of the system controller where you declare the submachines, also in the declarative region, declare the signals to connect them.
SIGNAL c1,c2,c3 : BIT;
Oct 26, 2008
ECE Lecture 14 - System Controller

10. ECE 561 - Lecture 14 - System Controller
A seconds counter
The ENTITY
ENTITY secs IS
PORT ( clk : IN BIT;
reset_sec : IN BIT;
secs : OUT BIT_VECTOR(5 downto 0) );
END secs;
Oct 26, 2008
ECE Lecture 14 - System Controller

11. ECE 561 - Lecture 14 - System Controller
The ARCHITECTURE
ARCHITECTURE one OF secs IS
SIGNAL inext_sec, isec : BIT_VECTOR(5 downto 0);
SIGNAL incrnext_sec : BIT_VECTOR(5 downto 0);
SIGNAL incr_sec_carry : BIT_VECTOR(6 downto 0) := “ ”; --note initialization
BEGIN
Notes: need the signal for current and next state
incrnext_sec if the value of isec (internal seconds) plus 1 to choose from for input to the F/Fs
Oct 26, 2008
ECE Lecture 14 - System Controller

12. ECE 561 - Lecture 14 - System Controller
The F/F Process
Here the F/F will latch the 6 bit value of the counter
-- F/F process
PROCESS
BEGIN
WAIT UNTIL (clk = ‘1’ and clk’event);
isec <= inext_sec;
END PROCESS:
Oct 26, 2008
ECE Lecture 14 - System Controller

13. The Next state generation
Cannot do a binary adder within a process
Need to use concurrent signals assignment statements for it.
If A and B are 4 bits then addition of A and B looks like
Oct 26, 2008
ECE Lecture 14 - System Controller

14. ECE 561 - Lecture 14 - System Controller
In VHDL
For an increment the B input is 0 and can be set to such.
So we have
SUM = A xor B xor C = A xor C when B =0
For each bit position
Ci+1 = Ai•Ci
Vector wise we have, n being number of bits
C(n:1) = A(n-1:0) and C(n-1:0);
and having set C(0) = ‘1’ which is done in the declaration of the vector through initialization.
Oct 26, 2008
ECE Lecture 14 - System Controller

15. So here next state code is
incrnext_sec <= isec xor incr_sec_carry(5 downto 0);
incr_sec_carry(6 downto 1) <= isec AND incr_sec_carry(5 downto 0);
-- process the select input for F/Fs
PROCESS
BEGIN
IF (reset = ‘0 or incrnext_sec = “111100’)
THEN inext_sec <= “000000”;
ELSE
inext_sec <= incrnext_sec;
END IF;
END PROCESS;
Oct 26, 2008
ECE Lecture 14 - System Controller

16. ECE 561 - Lecture 14 - System Controller
No real output Logic
Simply need to connect to the output port for output
secs <= isec;
-- and then end the architecture
END one;
Oct 26, 2008
ECE Lecture 14 - System Controller

17. To use this in higher level unit
ARCHITECTURE one OF alarmclk IS
COMPONENT secs
PORT ( clk : IN BIT;
reset_sec : IN BIT;
secs : OUT BIT_VECTOR(5 downto 0));
END COMPONENT;
-- configure Not sure if need in XILINX
FOR all : secs USE ENTITY work.secs(one);
and then other delcarations
BEGIN
Oct 26, 2008
ECE Lecture 14 - System Controller

18. ECE 561 - Lecture 14 - System Controller
TO use
BEGIN
-- instantiate component
C0 : secs PORT MAP (clk,reset,secs);
Oct 26, 2008
ECE Lecture 14 - System Controller

19. ECE 561 - Lecture 14 - System Controller
Oct 26, 2008
ECE Lecture 14 - System Controller

20. ECE 561 - Lecture 14 - System Controller
Oct 26, 2008
ECE Lecture 14 - System Controller