1. Day 25: November 8, 2010 Memory Core
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 25: November 8, 2010
Memory Core
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2. Today 6T SRAM review 5T SRAM Multiport SRAM DRAM Leakage
Charge sharing
Precharge
Multiport SRAM
DRAM
Leakage
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3. Memory Bank
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4. SRAM Memory bit
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5. Memory Bank
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6. 5T SRAM
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7. Consider What happens to voltage at A when WL turns from 01
Assume Waccess large
Waccess >> Wpu=1
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8. Voltage After enable Word Line
QBL = 0
QA = (1V)(g(2+Waccess)C0)
CBL>>CA=(g(2+Waccess)C0)
After enable Waccess
Total charge roughly unchanged
Distributed over larger capacitance~=CBL
VA=VBL~= CA/CBL
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9. Larger Resistance? What happens if Waccess small? Waccess < Wpu
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10. Simulation: Waccess=100
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11. Simulation
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12. Charge Sharing Charge sharing can pull down voltage
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13. Consider What happens to voltage at A when WL turns from 01
Assume Waccess large
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14. Simulation Waccess=20
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15. Simulation Waccess=4
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16. Charge Sharing Charge sharing can lead to read upset
Charge redistribution adequate to flip state of bit
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17. How might we avoid?
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18. Precharge to middle Voltage
Precharge to Vdd/2
Now charge sharing doesn’t swing to opposite side of midpoint
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19. Simulation Waccess=20
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20. Multiport RAM
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21. Mulitport Perform multiple operations simultaneously
E.g. Processor register file
R3R1+R2
Requires two reads and one write
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22. Simple Idea
Add access transistors
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23. Watch? What do we need to be careful about?
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24. Isolate BL form Mem Larger, but more robust
Essential for large # of read ports
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25. Adding Write Port
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26. Write Port
What options does this raise?
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27. Opportunity Asymmetric cell size Separate sizing constraints
Weak drive into write port (Wrestore)
Strong drive into read port (Wbuf)
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28. Multiple Write Ports
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29. DRAM
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30. 1T 1C DRAM Simplest case – Memory is capacitor
Feature of DRAM process is ability to make large capacitor compactly
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31. 1T DRAM What happens when read this cell?
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32. 1T DRAM On read, charge sharing Small swing on bit line
VBL = (Cbit/CBL)Vstore
Small swing on bit line
Must sense
Means want large Cbit
Limits bits/bitline so VBL large enough
Cell always depleted on read
Must be rewritten
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33. Dynamic RAM Takes sharing idea one step further
Share refresh/restoration logic as well
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34. 3T DRAM
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35. 3T DRAM
How does this work?
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36. 3T DRAM Correct operation not sensitive to sizing
Does not deplete cell on read
No charge sharing with stored state
Must use Vdd+VTN on BL to write full voltage
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37. Some Numbers (memory) Register as stand-alone element  4Kl2
Static RAM cell  1Kl2
SRAM Memory (single ported)
Dynamic RAM cell (DRAM process)  100l2
Dynamic RAM cell (SRAM process)  300l2
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38. Energy
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39. Single Port Memory What are most cells doing on a cycle?
What fraction is involved in a read/write?
When not doing a read or write?
Reads are slow
Cycles long  lots of time to leak
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40. ITRS 2009 45nm C0 = 0.045mm × Cg,total High Performance Low Power
Isd,leak
100nA/mm
50pA/mm
Isd,sat
1200 mA/mm
560mA/mm
Cg,total
1fF/mm
0.91fF/mm
Vth
285mV
585mV
C0 = 0.045mm × Cg,total
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41. High Power V=1V d=1000 g=0.5 Full swing for simplicity Csc = 0
(just for simplicity, typically <Cload)
Cload=1000C0 ≈ 45 fF = 45×10-15F
WN = 2  Ileak = 9×10-9 A
P= (45×10-15) freq ×9×10-9 W
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42. Relative Power P= (45×10-15) freq + 1000×9×10-9 W
Break even at freq=200MHz
Partial swing on bit line
Reduce dynamic energy
Increase percentage in leakage energy
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43. Consequence Leakage energy can dominate in large memories
Care about low operating (or stand-by) power
Use process with high Vth
Reduce leakage at expense of speed
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44. Admin Size your memory cell André office hours Tuesday
Andrew office hours Wednesday and Thursday
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45. Idea Memory can be compact Rich design space Demands careful sizing
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