1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. Serial Adder CprE 281: Digital Logic Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff Homework 10 is out
It is due on Monday Nov 17, 2014

4. Quick Review

5. (there are four possible cases)
Adding two bits
(there are four possible cases)
[ Figure 3.1a from the textbook ]

6. Adding two bits (the truth table)
[ Figure 3.1b from the textbook ]

7. Adding two bits (the logic circuit)
[ Figure 3.1c from the textbook ]

8. The Half-Adder
[ Figure 3.1c-d from the textbook ]

9. Addition of multibit numbers
Bit position i
[ Figure 3.2 from the textbook ]

10. Problem Statement and Truth Table
[ Figure 3.2b from the textbook ]
[ Figure 3.3a from the textbook ]

11. Let’s fill-in the two K-maps
[ Figure 3.3a-b from the textbook ]

12. Let’s fill-in the two K-maps
[ Figure 3.3a-b from the textbook ]

13. The circuit for the two expressions
[ Figure 3.3c from the textbook ]

14. This is called the Full-Adder
[ Figure 3.3c from the textbook ]

15. XOR Magic

16. XOR Magic

17. XOR Magic
Can you prove this?

18. (si can be implemented in two different ways)
XOR Magic
(si can be implemented in two different ways)

19. A decomposed implementation of the full-adder circuitHA c x i HA c c y i + 1 i
(a) Block diagram c i s i x i y i c i + 1
(b) Detailed diagram
[ Figure 3.4 from the textbook ]

20. The Full-Adder AbstractionHA c x i c i 1 + HA c y i

21. The Full-Adder AbstractionFA x i c i 1 + y i

22. We can place the arrows anywherexi yi
ci+1 FA ci si

23. n-bit ripple-carry adderx y x y x y
n – 1 n – 1 1 1 c 1 c c n FA c n ” 1 2 FA FA c s s s n – 1 1
MSB position
LSB position
[ Figure 3.5 from the textbook ]

24. n-bit ripple-carry adder abstractionx y x y x y
n – 1 n – 1 1 1 c 1 c c n FA c c n ” 1 2 FA FA s s s n – 1 1
MSB position
LSB position

25. n-bit ripple-carry adder abstractionx y x y x y
n – 1 n – 1 1 1 c c n s s s n – 1 1

26. The x and y lines are typically
grouped together for better visualization,
but the underlying logic remains the same x
n – 1 c n y – s

27. Serial Adder
The n-bit adder requires all bits to be provided at the same time.
In some cases we may want to add the numbers as the bits come in.
Also, with an n-bit adder we are limited to n-bits. Circuits for larger n are more complex.
Can we add arbitrarily long numbers.

28. Block diagram for the serial adder
Shift register s
Adder
FSM
Shift register
Shift register b
Sum = A + B B
Clock
[ Figure 6.39 from the textbook ]

29. State diagram for the serial adder FSM
[ Figure 6.40 from the textbook ]

30. State diagram for the serial adder FSM
[ Figure 6.40 from the textbook ]

31. State diagram for the serial adder FSM
[ Figure 6.40 from the textbook ]

32. State diagram for the serial adder FSM

33. State diagram for the serial adder FSM

34. State diagram for the serial adder FSM

35. State diagram for the serial adder FSM

36. State diagram for the serial adder FSM

37. State diagram for the serial adder FSM

38. State diagram for the serial adder FSM

39. State diagram for the serial adder FSM

40. State diagram for the serial adder FSM
State table for the serial adder FSM
Present
Next state
Output s
state ab
=00 01 10 11 00 G H 1
[ Figure 6.40 & 6.41 from the textbook ]

41. State diagram for the serial adder FSM
State table for the serial adder FSM
Present
Next state
Output s
state ab
=00 01 10 11 00 G H 1
[ Figure 6.40 & 6.41 from the textbook ]

42. State diagram for the serial adder FSM
State table for the serial adder FSM
Present
Next state
Output s
state ab
=00 01 10 11 00 G H 1
[ Figure 6.40 & 6.41 from the textbook ]

43. State table for the serial adder FSM
Present
Next state
Output s
state ab
=00 01 10 11 00 G H 1
[ Figure 6.41 from the textbook ]

44. State table for the serial adder FSM
Present
Next state
Output s
state ab
=00 01 10 11 00 G H 1
State-assigned table for the serial adder
Present
Next state
Output
state ab
=00 01 10 11 00 y Y s 1
[ Figure 6.41 & 6.42 from the textbook ]

45. State table for the serial adder FSM
Present
Next state
Output s
state ab
=00 01 10 11 00 G H 1
State-assigned table for the serial adder
Present
Next state
Output
state ab
=00 01 10 11 00 y Y s 1
[ Figure 6.41 & 6.42 from the textbook ]

46. State table for the serial adder FSM
Present
Next state
Output s
state ab
=00 01 10 11 00 G H 1
State-assigned table for the serial adder
Present
Next state
Output
state ab
=00 01 10 11 00 y Y s 1
[ Figure 6.41 & 6.42 from the textbook ]

47. Derivation of Y and s Present Next state Output state ab =00 01 10 111

48. Derivation of Y and s Present Next state Output state ab =00 01 10 111 y a b Y s 1

49. Derivation of Y and s Present Next state Output state ab =00 01 10 111 y a b Y s 1

50. Derivation of Y and s Present Next state Output state ab =00 01 10 111 y a b Y s 1 b 00 01 11 10 1 y a Y b 00 01 11 10 1 y a s

51. Derivation of Y and s Present Next state Output state ab =00 01 10 111 y a b Y s 1 b 00 01 11 10 1 y a Y b 00 01 11 10 1 y a s

52. Derivation of Y and s Present Next state Output state ab =00 01 10 111 y a b Y s 1 b 00 01 11 10 1 y a Y b 00 01 11 10 1 y a s

53. Derivation of Y and s Y = ab + ay + by s = XOR(XOR(a, b), y) Present
Next state
Output
state ab
=00 01 10 11 00 y Y s 1 y a b Y s 1 b 00 01 11 10 1 y a Y b 00 01 11 10 1 y a s
Y = ab + ay + by
s = XOR(XOR(a, b), y)

54. Circuit for the serial adder FSM
Full b
adder Y y D Q
carry-out
Clock Q
Reset
Y = ab + ay + by
s = XOR(XOR(a, b), y)
[ Figure 6.43 from the textbook ]

55. Moore Machine Implementation

56. State diagram for the Moore-type serial adder FSM1 s =
Reset 01 10 11 G 00
[ Figure 6.44 from the textbook ]

57. State diagram for the Moore-type serial adder FSM1 s =
Reset 01 10 11 G 00
carry=0, sum=0
carry=1, sum=0
carry=0, sum=1
carry=1, sum=1
[ Figure 6.44 from the textbook ]

58. State diagram for the Moore-type serial adder FSM1 s =
Reset 01 10 11 G 00
carry=0, sum=0
carry=1, sum=0
carry=0, sum=1
carry=1, sum=1
[ Figure 6.44 from the textbook ]

59. State table for the Moore-type serial adder FSM
Present
Nextstate
Output
state ab
=00 01 10 11 s G 1 H H 1 s =
Reset 01 10 11 G 00
[ Figure 6.45 from the textbook ]

60. State table for the Moore-type serial adder FSM
Present
Nextstate
Output
state ab
=00 01 10 11 s G 1 H
[ Figure 6.45 from the textbook ]

61. State table for the Moore-type serial adder FSM
Present
Nextstate
Output
state ab
=00 01 10 11 s G 1 H
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00
[ Figure 6.45 & 6.46 from the textbook ]

62. State table for the Moore-type serial adder FSM
Present
Nextstate
Output
state ab
=00 01 10 11 s G 1 H
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00
[ Figure 6.45 & 6.46 from the textbook ]

63. for the Moore-type serial adder FSM
State-assigned table
for the Moore-type serial adder FSM
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00
[ Figure 6.46 from the textbook ]

64. Deriving Y1, Y2, and s Present Nextstate state ab =00 01 10 11 Output1
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00

65. Deriving Y1 Present Nextstate state ab =00 01 10 11 Output y Y s 00 21
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00

66. Deriving Y1 Present Nextstate state ab =00 01 10 11 Output y Y s 00 21
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00

67. Deriving Y1 Present Nextstate state ab =00 01 10 11 Output y Y s 00 21
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00 00 01 11 10 y 2 1
a b

68. Deriving Y1 Present Nextstate state ab =00 01 10 11 Output y Y s 00 21
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00 00 01 11 10 1 y 2
a b

69. Deriving Y1 Y1 = a + b + y2 Present Nextstate state ab =00 01 10 111
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00 00 01 11 10 1 y 2
a b
Y1 = a + b + y2

70. Deriving Y2 Present Nextstate state ab =00 01 10 11 Output y Y s 00 21
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00

71. Deriving Y2 Present Nextstate state ab =00 01 10 11 Output y Y s 00 21
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00

72. Deriving Y2 Present Nextstate state ab =00 01 10 11 Output y Y s 00 21
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00 00 01 11 10 y 2 1
a b

73. Deriving Y2 Present Nextstate state ab =00 01 10 11 Output y Y s 00 21
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00 00 01 11 10 1 y 2
a b

74. Deriving Y2 Present Nextstate state ab =00 01 10 11 Output y Y s 00 21
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00 00 01 11 10 1 y 2
a b

75. Deriving Y2 Y2 = ab + ay2 + by2 Present Nextstate state ab =00 01 101
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00 00 01 11 10 1 y 2
a b
Y2 = ab + ay2 + by2

76. Deriving s Present Nextstate state ab =00 01 10 11 Output y Y s 00 2 1y2 y1 s 1

77. Deriving s Present Nextstate state ab =00 01 10 11 Output y Y s 00 2 1y2 y1 s 1

78. Deriving s Present Nextstate state ab =00 01 10 11 Output y Y s 00 2 1y2 y1 s 1 1 y 2 s

79. Deriving s Present Nextstate state ab =00 01 10 11 Output y Y s 00 2 1y2 y1 s 1 1 y 2 s

80. Deriving s s = y1 Present Nextstate state ab =00 01 10 11 Output y Y s2 1 Y s 00 y2 y1 s 1 1 y 2 s
s = y1

81. for the Moore-type serial adder FSM
State-assigned table
for the Moore-type serial adder FSM
Present
Nextstate
state ab
=00 01 10 11
Output y 2 1 Y s 00
Y1 = a + b + y2
Y2 = ab + ay2 + by2
s = y1
[ Figure 6.46 from the textbook ]

82. Circuit for the Moore-type serial adder FSM
Full
adder a b D Q
Carry-out
Clock
Reset s Y 2 1
Sum bit y
Y1 = a + b + y2
(sum from FA)
Y2 = ab + ay2 + by2
(carry from FA)
s = y1
[ Figure 6.47 from the textbook ]

83. Questions?

84. THE END