1. 디 지 털 시 스 템 설 계 UP2 Kit를 이용한 카운터 설계
충 북 대 학 교
송 기 용

3. Clock 설계 library ieee; use ieee.std_logic_1164.all;
entity clockdiv is port (
clk25mhz: in std_logic;
clk: out std_logic);
end clockdiv;
architecture rtl of clockdiv is
constant max: integer := ;
constant half: integer := max/2;
signal count: integer range 0 to max;
begin
process
wait until clk25mhz'event and clk25mhz = '1';
if count < max then
count <= count + 1;
else
count <= 0;
end if;
if count < half then
clk <= '0';
clk <= '1';
end process;
end rtl;

4. decoder 설계 library ieee; use ieee.std_logic_1164.all;
entity decoder is port (
i: in std_logic_vector(3 downto 0); bit input to decoder
an,bn,cn,dn,en,fn,gn: out std_logic); -- the 7-segment outputs "abcdefg"
end decoder;
architecture rtl of decoder is
signal segments: std_logic_vector(1 to 7);
begin
process(i)
case i is
when "0000" => segments <= " "; a 1 turns on the led
when "0001" => segments <= " "; -- 1
when "0010" => segments <= " "; -- 2
when "0011" => segments <= " "; -- 3
when "0100" => segments <= " "; -- 4
when "0101" => segments <= " "; -- 5
when "0110" => segments <= " "; -- 6
when "0111" => segments <= " "; -- 7
when "1000" => segments <= " "; -- 8
when "1001" => segments <= " "; -- 9
when "1010" => segments <= " "; -- a
when "1011" => segments <= " "; -- b
when "1100" => segments <= " "; -- c
when "1101" => segments <= " "; -- d
when "1110" => segments <= " "; -- e
when "1111" => segments <= " "; -- f
when others => segments <= " "; -- all off
end case;
end process;
an <= not segments(1);
bn <= not segments(2);
cn <= not segments(3);
dn <= not segments(4);
en <= not segments(5);
fn <= not segments(6);
gn <= not segments(7);
end rtl

5. counter 설계 library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is port (
clock: in std_logic; input clock source
clear: in std_logic; clear counter to 0
count: in std_logic; to count
q: out std_logic_vector(3 downto 0); -- output of the counter
overflow: out std_logic);
end counter;
architecture rtl of counter is
signal countvalue: std_logic_vector(3 downto 0); to remember the count as a 4-bit value
begin
process(clock,clear,count)
if (clear = '1' ) then
countvalue <= "0000"; reset the count to 0 when resetn is low
elsif (clock'event and clock = '1') then
if (count = '1') then
countvalue <= countvalue + "0001"; -- increment the count by 1
end if;
end process;
overflow <= '1' when countvalue = "1111" else '0';
q <= countvalue; assign the count to the counter output
end rtl;

6. upflex 설계 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
ENTITY up2flex IS PORT (
Clock_25MHz: IN STD_LOGIC;
ResetN: IN STD_LOGIC;
StopN: IN STD_LOGIC;
aN,bN,cN,dN,eN,fN,gN,Overflow: OUT STD_LOGIC;
Vcc: OUT STD_LOGIC_VECTOR(1 TO 8));
END up2flex;
ARCHITECTURE structural OF up2flex IS
-- declares the three components to use
COMPONENT Clockdiv PORT (
Clk25Mhz: IN STD_LOGIC;
Clk: OUT STD_LOGIC);
END COMPONENT;
COMPONENT Counter PORT (
Clock: IN STD_LOGIC;
Clear: IN STD_LOGIC;
Count: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Overflow: OUT STD_LOGIC);
END COMPONENT;
COMPONENT Decoder PORT (
I: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
aN,bN,cN,dN,eN,fN,gN: OUT STD_LOGIC);
-- internal signals for doing the connections between the components
SIGNAL Clock,Reset,Over: STD_LOGIC;
SIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
-- use structural level coding to connect the three components together
U0: Clockdiv PORT MAP (Clock_25MHz,Clock);
U1: Counter PORT MAP (Clock,Reset,StopN,Q,Over);
U2: Decoder PORT MAP (Q,aN,bN,cN,dN,eN,fN,gN);
Reset <= NOT ResetN;
Overflow <= NOT over;
Vcc <= " ";
END structural;

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