1. CSE 370 – Winter 2002 - Sequential Logic-2 - 1
Overview
Last lecture
Example: Ant in a maze
More on Moore vs. Mealy
Today
Optimization of FSMs
State assignment
8/2/2019
CSE 370 – Winter Sequential Logic-2 - 1

2. Vending machine implementation
D1 = Q1 + D + Q0 N
D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0
8/2/2019
CSE 370 – Winter Sequential Logic-2 - 2

3. Map design to a (registered) PLD
reset
COM out
CLK
D Q Q' Q0 Q1
REG out N
OPEN
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CSE 370 – Winter Sequential Logic-2 - 3

4. CSE 370 – Winter 2002 - Sequential Logic-2 - 4
Retime design
OPEN is delayed by AND gate after Q1 and Q0
Can remove this delay by retiming
Move output logic (AND gate) to eliminate delay
OPEN = Q1Q0 = (Q1+D+Q0N)(Q0'N+Q0N'+Q1N+Q1D)
Original Design Retimed Design
8/2/2019
CSE 370 – Winter Sequential Logic-2 - 4

5. Retimed PLD implementation
CLK
D Q Q' Q0 Q1
REG out N D
reset
OPEN
8/2/2019
CSE 370 – Winter Sequential Logic-2 - 5

6. Synchronous (or registered) Mealy machine
Moore machine with no output decoding (like the retimed Moore vending machine)
Registered state and registered outputs
No glitches on outputs
No race conditions between communicating machines
reg
inputs
combinational logic for outputs and next state
outputs
reg
state feedback
8/2/2019
CSE 370 – Winter Sequential Logic-2 - 6

7. Finite state machine optimization
State minimization
fewer states require fewer state bits
fewer bits require fewer logic equations
Encodings: state, inputs, outputs (affects speed and size of FSM)
State code is a vector: log(n) to n bits (n  # of states)
trade flip-flop count for logic complexity
state encoding with fewer bits has fewer equations to implement
however, each may be more complex
state encoding with more bits (e.g., one-hot) has simpler equations
complexity directly related to complexity of state diagram
input/output encoding may or may not be under designer control
8/2/2019
CSE 370 – Winter Sequential Logic-2 - 7

8. Algorithmic approach to state minimization
Goal – identify and combine states that have equivalent behavior
Equivalent states:
same output
for all input combinations, states transition to same or equivalent states
Algorithm sketch
1. place all states in one set
2. initially partition set based on output behavior
3. successively partition resulting subsets based on next state transitions
4. repeat (3) until no further partitioning is required
states left in the same set are equivalent
polynomial time procedure
8/2/2019
CSE 370 – Winter Sequential Logic-2 - 8

9. State minimization example
Sequence detector for 010 or 110 (e.g. input yields output )
Input Next State Output
Sequence Present State X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
Notice the short-hand notation for the transition table S0 S3 S2 S1 S5 S6 S4
1/0
0/0
0/1
8/2/2019
CSE 370 – Winter Sequential Logic-2 - 9

10. Method of successive partitions
Input Next State Output
Sequence Present State X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
( S0 S1 S2 S3 S4 S5 S6 )
( S0 S1 S2 S3 S5 ) ( S4 S6 )
( S0 S1 S1 ) ( S3 S5 ) ( S4 S6 )
( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )
S4 is equivalent to S6
S3 is equivalent to S5
S1 is equivalent to S2
Polynomial time algorithm
8/2/2019
CSE 370 – Winter Sequential Logic

11. CSE 370 – Winter 2002 - Sequential Logic-2 - 11
Minimized FSM
State minimized sequence detector for 010 or 110
Input Next State Output
Sequence Present State X=0 X=1 X=0 X=1
Reset S0 S1' S1' 0 0
0 + 1 S1' S3' S4' 0 0
X0 S3' S0 S0 0 0
X1 S4' S0 S0 1 0 S0
S1’
S3’
S4’
X/0
1/0
0/1
0/0
This method does not always yield the minimum number of states: easy to find counter examples
8/2/2019
CSE 370 – Winter Sequential Logic

12. Example: Complex state diagram
symbolic state-transition table 10 01 11 00
S0 [1]
S2 [1]
S4 [1] S1
[0] S3 S5
inputs
present next state output state S0 S0 S1 S2 S S1 S0 S3 S1 S S2 S1 S3 S2 S S3 S1 S0 S4 S S4 S0 S1 S2 S S5 S1 S4 S0 S5 0
8/2/2019
CSE 370 – Winter Sequential Logic

13. CSE 370 – Winter 2002 - Sequential Logic-2 - 13
Minimized FSM
Implication chart method (enumerates all possible combinations of states taken 2 at a time) (1) cross out incompatible states based on outputs (2) cross out more cells if indexed chart entries are already crossed out S1 S2 S3 S4 S5 S0
minimized state table
(S0==S4) (S3==S5)
present next state output state S0' S0' S1 S2 S3' S1 S0' S3' S1 S3' S2 S1 S3' S2 S0' S3' S1 S0' S0' S3' 0
S0-S1
S1-S3
S2-S2
S3-S4
S0-S1
S3-S0
S1-S4
S4-S5
S0-S0
S1-S1
S2-S2
S3-S5
S1-S0
S3-S1
S2-S2
S4-S5
Polynomial time algorithm
S0-S1
S3-S4
S1-S0
S4-S5
S4-S0
S5-S5
S1-S1
S0-S4
8/2/2019
CSE 370 – Winter Sequential Logic

14. Minimizing incompletely specified FSMs
State equivalence is transitive for fully specified machines
But is not transitive if some states are “don't cares”
e.g., state output S0 – S1 is compatible with both S0 and S2 S1 1 – but S0 and S2 are incompatible S2 – 1
No polynomial time algorithm for determining the state grouping that gives the smallest number of final states
8/2/2019
CSE 370 – Winter Sequential Logic

15. Minimizing states may not yield best circuit
Example: edge detector - outputs 1 when last two input changes from 0 to 1
X Q1 Q0 Q1+ Q –
00 [0] 10
[0]
01 [1] X’ X
Q1+ = X (Q1 xor Q0)
Q0+ = X Q1 Q0
8/2/2019
CSE 370 – Winter Sequential Logic

16. Another implementation of edge detector
"Ad hoc" solution - not minimal but cheap and fast
00 [0] 10
[0]
01 [1] X’ X
11 [0]
8/2/2019
CSE 370 – Winter Sequential Logic